- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98293 > TS8308500CG (ATMEL CORP) 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 PDF資料下載
參數(shù)資料
| 型號： | TS8308500CG |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| 封裝： | 1.27 MM PITCH, HEAT SINK, CERAMIC, BGA-72 |
| 文件頁數(shù)： | 3/42頁 |
| 文件大小： | 641K |
| 代理商： | TS8308500CG |
第1頁第2頁當前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
11
Preliminary Specification
ββββ-site
TS8308500
4.
PACKAGE DESCRIPTION.
4.1.
TS8308500 PAD DESCRIPTION
Pad
number
Chip pad
Name
Chip Pad Function
1VPLUSD
Positive digital supply
(double pad) (note 2)
2
D5
In phase (+) digital output, bit 5
(D7 is the MSB ; Bit 7, D0 is the LSB ; Bit 0)
3
D5B
Inverted phase (-)digital output, bit 5
4
D4
In phase (+) digital output, bit 4
5
D4B
Inverted phase (-) digital output, bit 4
6DVEE
-5V digital supply
(double pad)
7
DR
In phase (+) Data Ready
8
DRB
Inverted Phase (-) Data Ready
9
D3
In phase (+) digital output, bit 3
10
D3B
Inverted phase (-) digital output, bit 3
11
VPLUSD
Positive digital supply
(double pad) (note 2)
12
D2
In phase (+) digital output, bit 2
13
D2B
Inverted phase (-) digital output, bit 2
14
D1
In phase (+) digital output, bit 1
15
D1B
Inverted phase (-) digital output, bit 1
16
D0
In phase (+) digital output, bit 0, Least Significant Bit
17
D0B
Inverted phase (-) digital output, bit 0, Least Significant Bit
18
GORB
Gray or Binary data output format select.
(Note 1)
19
VCC
+5V supply
(double pad)
20
GND
Analog Ground
(double pad)
21
VCC
+5V supply
(double pad)
22
VEE
-5V analog supply
(double pad)
23
VCC
+5V supply
(double pad)
24
GND
Analog Ground
(double pad)
25
CLK
In phase (+) clock input
(double pad)
26
GND
Analog Ground
27
CLKB
Inverted phase (-) clock input
(double pad)
28
GND
Analog Ground
(double pad)
29
VEE
-5V analog supply
(double pad)
30
VCC
+5V supply
(double pad)
31
VEE
-5V analog supply
(double pad)
32
DIOD/DRRB
Diode input for Tj monitoring / Input for asynchronous Data Ready Reset
33
GND
Analog Ground
34
VIN
In phase (+) analog input
(double pad)
35
GND
Analog Ground
36
VINB
Inverted phase (-) analog input
(double pad)
37
GND
Analog Ground
(double pad)
38
GAIN
ADC gain adjust input
39
VCC
+5V supply
(double pad)
40
VCC
+5V supply
41
OR
In phase (+) Out of Range digital output
42
ORB
Inverted phase (-) Out of Range digital output
43
D7
In phase (+) digital output, bit 7, Most Significant Bit
44
D7B
Inverted phase (-) digital output bit 7
45
D6
In phase (+) digital output, bit 6
46
D6B
Inverted phase (-) digital output, bit 6
Note 1: GORB tied to Vcc or floating : Binary output data format. GORB tied to GND : Gray output data format
Note2: The common mode level of the output buffers is 1.2V below the positive digital supply.
For ECL compatibility the positive digital supply must be set at 0V (ground).
For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.
If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive digital
supply level in the name proportion in order to spare power dissipation.
相關PDF資料 |
PDF描述 |
|---|---|
| TS83102G0BMGS | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| TS83102G0BMGS | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| TS83102G0BVGL | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| TS83102G0BCGL | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| TS83110CZT | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDFP28 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TS8308500CGL | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:ADC 8-bit 500 Msps |
| TS8308500VGL | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:ADC 8-bit 500 Msps |
| TS8308C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| TS8308J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| TS8308P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
發(fā)布緊急采購，3分鐘左右您將得到回復。