參數(shù)資料
型號： TS80C52X2-VIBB
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 10/56頁
文件大?。?/td> 689K
代理商： TS80C52X2-VIBB
Rev. C - Aug. 31, 1999
18
TS80C52X2
6.4 TS80C52X2 Serial I/O Port
The serial I/O port in the TS80C52X2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous
Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and
reception can occur simultaneously and at different baud rates
Serial I/O port includes the following enhancements:
q
Framing error detection
q
Automatic address recognition
6.4.1 Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing
bit error detection feature, set SMOD0 bit in PCON register (See Figure 6).
Figure 6. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop
bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit
is not found, the Framing Error bit (FE) in SCON register (See Table 8.) bit is set.
RI
TI
RB8
TB8
REN
SM2
SM1
SM0/FE
IDL
PD
GF0
GF1
POF
-
SMOD0
SMOD1
To UART framing error control
SM0 to UART mode control (SMOD = 0)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SCON (98h)
PCON (87h)
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