參數(shù)資料
型號(hào)： TS80C52X2-VCCD
英文描述： 8-bit CMOS Microcontroller 0-60 MHz
中文描述： 8位CMOS微控制器0-60兆赫
文件頁(yè)數(shù)： 36/54頁(yè)
文件大?。?/td> 626K
代理商： TS80C52X2-VCCD
Rev. B - Jan. 25, 1999
41
Preliminary
TS80C52X2
10.3 DC Parameters for Low Voltage
TA =0
°Cto+70°C; V
SS =0V;VCC = 2.7 V to 5.5 V ± 10%;F=0to30 MHz.
TA = -40
°Cto+85°C; V
SS =0V;VCC = 2.7 V to 5.5 V ± 10%;F=0to30 MHz.
Table 23. DC Parameters for Low Voltage
NOTES
1.
Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 16.), VIL = VSS + 0.5 V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used..
2.
Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH,TCHCL = 5 ns, VIL =VSS + 0.5 V, VIH =VCC - 0.5 V; XTAL2
N.C; Port 0 = VCC; EA = RST = VSS (see Figure 14.).
3.
Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 15.).
4.
Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is
due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5.
Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.
6.
Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specication. Pins are not guaranteed to sink current greater than the listed test conditions.
7.
For other values, please contact your sales ofce.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIL
Input Low Voltage
-0.5
0.2 VCC - 0.1
V
VIH
Input High Voltage except XTAL1, RST
0.2 VCC + 0.9
VCC + 0.5
V
VIH1
Input High Voltage, XTAL1, RST
0.7 VCC
VCC + 0.5
V
VOL
Output Low Voltage, ports 1, 2, 3 (6)
0.45
V
IOL = 0.8 mA
(4)
VOL1
Output Low Voltage, port 0, ALE, PSEN (6)
0.45
V
IOL = 1.6 mA
(4)
VOH
Output High Voltage, ports 1, 2, 3
0.9 VCC
V
IOH = -10 A
VOH1
Output High Voltage, port 0, ALE, PSEN
0.9 VCC
V
IOH = -40 A
IIL
Logical 0 Input Current ports 1, 2 and 3
-50
A
Vin = 0.45 V
ILI
Input Leakage Current
±10
A
0.45 V < Vin < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3
-650
A
Vin = 2.0 V
RRST
RST Pulldown Resistor
50
90 (5)
200
k
CIO
Capacitance of I/O Buffer
10
pF
Fc = 1 MHz
TA = 25
°C
IPD
Power Down Current
TBD (5)
TBD
A
VCC = 2.0 V to 5.5 V
(3)
ICC
Power Supply Current (7)
Active Mode 16MHz
Idle Mode
16MHz
TBD (5)
TBD
mA
VCC = 3.3 V
(1)
VCC = 3.3 V
(2)
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