參數(shù)資料
型號(hào)： TS80C51RD2-MCBB
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 6/74頁
文件大?。?/td> 689K
代理商： TS80C51RD2-MCBB
14
Rev. C - 06 March, 2001
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
6.2. Dual Data Pointer Register Ddptr
The additional data pointer can be used to speed up code execution and reduce code size in a number of
ways.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory
location. There are two 16-bit DPTR registers that address the external memory, and a single bit called
DPS = AUXR1/bit0 (See Table 4.) that allows the program code to switch between them (Refer to Figure 3).
Figure 3. Use of Dual Pointer
Table 4. AUXR1: Auxiliary Register 1
Application
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for
example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’
pointer and the other one as a "destination" pointer.
AUXR1
Address 0A2H
-
GF3
-
DPS
Reset value
X
0
X
0
Symbol
Function
-
Not implemented, reserved for future use.a
a.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new feature. In that case, the reset value of the new bit will be 0, and its active
value will be 1. The value read from a reserved bit is indeterminate.
b.
GF3 will not be available on first version of the RC devices.
DPS
Data Pointer Selection.
DPS
Operating Mode
0
DPTR0 Selected
1
DPTR1 Selected
GF3
This bit is a general purpose user flagb.
External Data Memory
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
0
7
DPTR0
DPTR1
相關(guān)PDF資料
PDF描述
TS83C51RB2ZZZ-VCBB 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PQCC44
TS80C51RD2-MCLB 8-BIT, 40 MHz, MICROCONTROLLER, PQCC68
TS83C51RB2ZZZ-LCEB 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP44
TS87C51RD2-MIMB 8-BIT, OTPROM, 40 MHz, MICROCONTROLLER, PQFP64
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