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Application Information
TS4973
15/19
Remark: This maximum value is only dependent
upon power supply voltage and load values.
The efficiency is the ratio between the output
power and the power supply
The maximum theoretical value is reached when
Vpeak = Vcc, so
3.5 Decoupling of the circuit
Two capacitors are needed to bypass properly the
TS4973. A power supply bypass capacitor CS and
a bias voltage bypass capacitor CB.
CS has particular influence on the THD+N in the
high frequency region (above 7kHz) and an
indirect influence on power supply disturbances.
With
1F,
you
can
expect
similar
THD+N
performances to those shown in the datasheet.
In the high frequency region, if CS is lower than
1F, it increases THD+N and disturbances on the
power supply rail are less filtered.
On the other hand, if CS is higher than 1F, those
disturbances on the power supply rail are more
filtered.
CB has an influence on THD+N at lower
frequencies, but its function is critical to the final
result of PSRR (with input grounded and in the
lower frequency region).
If CB is lower than 1F, THD+N increases at lower
frequencies and PSRR worsens.
If CB is higher than 1F, the benefit on THD+N at
lower frequencies is small, but the benefit to
PSRR is substantial.
Note that CIN has a non-negligible effect on PSRR
at lower frequencies. The lower the value of CIN,
the higher the PSRR.
3.6 Wake-up Time: TWU
TWU is directly linked to the size of the bypass
capacitor Cb. The slower the speed is, the higher
Cb is. When power supply is apply or standby
command
is
released,
output
amplifier
are
immediately un function. At this moment, the
charge of Cb begins and the internal bias voltage,
raise at the speed controlled by Cb. So, we define
the TWU when the internal bias voltage reaches
80% of the final value. With this condition, we can
write with Cb in F:
3.7 Shutdown time
When the standby command is set, the time to put
the two output stage in high impedance and the
internal circuitry in shutdown mode is a few
microseconds.
3.8 Pop and Click performance
Pop and Click performance is intimately linked
with the size of the input capacitor Cin and the
bias voltage bypass capacitor Cb.
Size of Cin is due to the lower cut-off frequency
and PSRR value requested. Size of Cb is due to
THD+N and PSRR requested always in lower
frequency.
Moreover, Cb determines the speed that the
amplifier turns ON. The slower the speed is, the
softer the turn ON noise is.
The charge time of Cb is directly proportional to
the internal generator resistance 350k
.
Then, the charge time constant for Cb is
τb = 350kxCb (s)
As Cb is directly connected to the non-inverting
input and if we want to minimize, in amplitude and
duration, the output spike on Vout1, Cin must be
charged faster than Cb. The charge time constant
of Cin is:
If Gs
≤ 0.4V: τin = 40000xCin
2 (s)
If Gs
≥ 1.5V: τin = RinxCin
1 (s)
Thus we have the relation
τin << τb (s)
The respect of this relation permits to minimize
the pop and click noise.
Remark: Minimize Cin and Cb has a benefit on
pop and click phenomena but also on cost and
size of the application.
3.9 Biasing of Cin1 and Cin2
An internal bias circuitry allow to keep Cin1 and
Cin2 always bias with the right DC value.
This circuitry eliminates all "possible clicks" when
gain select pin is used to switch for a gain to
another.
Vcc
4
V
ply
sup
P
PEAK
OUT
π
=
η
%
5
.
78
4
=
π
)
s
(
Cb
42
.
0
TWU ≈