參數(shù)資料
型號(hào)： TRF7960RHBR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁(yè)數(shù)： 13/52頁(yè)
文件大?。?/td> 1023K
代理商： TRF7960RHBR
SLOU186F – AUGUST 2006 – REVISED AUGUST 2010
www.ti.com
NOTE
The crystal oscillator’s two external shunt capacitor values are calculated based on the
crystal’s specified load capacitance. The external capacitors (connected to the OSC pins 30
and 31), are calculated as two capacitors in series plus CS (oscillator's gate internal
input/output capacitance plus PCB stray capacitance). The stray capacitance (CS) can be
estimated at approximately 5 ±2 pF (typical).
As an example, given a crystal with a required load capacitance (CL) of 18 pF,
CL = ((C1 × C2) / (C1 + C2)) + CS
18 pF = ((27 pF × 27 pF) / (27 pF + 27 pF)) + 4.5 pF
Hence, from this example, a 27-pF capacitor would be placed on pins 30 and 31 to ensure
proper crystal oscillator operation.
The transmit power level is selectable between half power of 100 mW (20 dBm) or full power of 200 mW
(23 dBm) when configured for 5-V automatic operation. The transmit output impedance is 8
when
configured for half power and 4
when configured for full power. Selection of the transmit power level is
set by bit B4 (rf_pwr) in the chip status control register (Table 5-9). When configured for 3-V automatic
operation, the transmit power level is typically selectable between 33 mW (15 dBm) in half-power mode
and 70 mW (18 dBm) in full-power mode (Vdd_RF at 3.3 V). Note that lower operating voltages result in
reduced transmit power levels.
In normal operation, the transmit modulation is configured by the selected ISO control register (address
01). External control of the transmit modulation is possible by setting the ISO control register (address 01)
to direct mode. While in direct mode, the transmit modulation is made possible by selecting the modulation
type ASK or OOK at pin 12. External control of the modulation type is made possible only if enabled by
setting B6 = 1 (en_ook_p) in the modulator and SYS_CLK control register (address 09). ASK modulation
depth is controlled by bits B0, B1 and B2 in the Modulator and SYS_CLK Control register (address 09).
The range of the ASK modulation is 7%–30%, or 100% (OOK).
The coding of the modulator and SYS_CLK control register is shown in Table 5-19.
The length of the modulation pulse is defined by the protocol selected in the ISO control register. With a
high-Q antenna, the modulation pulse is typically prolonged, and the tag detects a longer pulse than
intended. For such cases, the modulation pulse length can be corrected by using the TX pulse length
register. If the register contains all zeros, then the pulse length is governed by the protocol selection. If the
register contains a value other than 00h, the pulse length is equal to the value of the register in 73.7-ns
increments. This means the range of adjustment can be between 73.7 ns and 18.8 ms.
5.2.3.2
Transmitter - Digital
The digital portion of the transmitter is very similar to that of the receiver. Before beginning data
transmission, the FIFO should be cleared with a Reset command (0F). Data transmission is initiated with a
selected command (described in the Direct Commands section, Table 5-29). The MCU then commands
the reader to do a continuous Write command (3Dh, see Table 5-31) starting from register 1Dh. Data
written into register 1Dh is the TX length byte1 (upper and middle nibbles), while the following byte in
register 1Eh is the TX length byte2 (lower nibble and broken byte length). The TX byte length determines
when the reader sends the EOF byte. After the TX length bytes, FIFO data is loaded in register 1Fh with
byte storage locations 0 to 11. Data transmission begins automatically after the first byte is written into the
FIFO. The TX length bytes and FIFO can be loaded with a continuous-write command because the
addresses are sequential.
If the data length is longer than the allowable size of the FIFO, the external system (MCU) is warned when
the majority of data from the FIFO has already been transmitted by sending an interrupt request with a
flag in the IRQ register signaling FIFO low/high status. The external system should respond by loading the
next data packet into the FIFO.
20
System Description
Copyright 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TRF7960 TRF7961
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