TRC1300, TRC1315
MARCSTAR
I E/D
REMOTE CONTROL ENCODER/DECODERS
SLWS011D – AUGUST 1996 – REVISED JANUARY 1997
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
decoder mode (continued)
The TRC1300 and TRC1315 MARCSTAR I E/D devices are configured as a decoder by holding the CONF
terminal low
before the device is powered up (the device reads the CONF terminal during POR, power-on reset).
In the decoder mode, the device receives serial data from input terminal DIN/DOUT. The input data signal is
first passed through the internal amplifier/comparator for signal conditioning before being decoded and
compared with the four 40-bit security codes stored in EEPROM memory. When a match is found with
one or
more received data frames, the appropriate function output terminals, VRC/TX1 – VRC/TX4, are enabled
(active-low). The decoder activates a function output only when two identical function data packets are received
in the same frame. The function output remains active for a minimum period of 768 data clock cycles, which
can range from 154 ms to 1.54 seconds, depending on the clock frequency used. With a 1-KHz data clock rate,
for example, a function output is asserted for a minimum of 768 ms. The decoder keeps the appropriate function
output terminals (VRC/TX1 – VRC/TX4) active as long as it receives valid code, and through the blank time
between each frame, which is 150 clock cycles. The function outputs go inactive when invalid function data code
is received.
Configured as a decoder, the MARCSTAR I E/D samples the incoming serial data at 10 times the expected
transmitted data rate. As each symbol is sampled, an integrator determines if it represents a 1 or 0 by the total
number of high and low samples. A high symbol (110) has a high level for approximately two-thirds of the symbol
period, while a low symbol (100) is high for only one-third of the symbol period. Therefore, if five or more out
of eight of the samples are high, the symbol is decoded as a 1, and if three or fewer of the samples are high,
the symbol is decoded as a 0. The symbol format also improves synchronization of the decoder with the
incoming serial data. A transition from low to high always signifies the beginning of a symbol.
The method of synchronization employed by MARCSTAR I E/D uses a precode sync pattern that precedes the
security and function data portions of each frame sent by the encoder. The precode consists of 24 pulses with
a 50% duty cycle, each being high or low for one period of the data clock. This equates to a total of 48 bit times.
amplifier/comparator
A representation of the amplifier/comparator section of the MARCSTAR I E/D devices is shown in Figure 7. This
circuit is used to amplify and wave-shape low-level input signals to logic levels for input to the shift registers.
The internal R1 and C1 components combination form a reference-setting (autobias) network, and the time
constant of this network is about three symbols, or 12 bits of code. The internal components R2 and C2 form
a low-pass network with a time constant equal to approximately one-tenth of one DCLK period so that
high-frequency transients are attenuated before reaching the comparator.
_
+
_
+
R2
R1
C1
C2
To Shift
Registers
Amplifier/
Comparator
Unity-Gain
Buffer
IN
DIN/DOUT
Figure 7. Amplifier/Comparator Equivalent Schematic