參數(shù)資料
型號(hào): TPU3040PQ
廠(chǎng)商: MICRONAS SEMICONDUCTOR HOLDING AG
元件分類(lèi): 圖文
英文描述: TELETEXT DECODER, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 15/72頁(yè)
文件大?。?/td> 576K
代理商: TPU3040PQ
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
22
3.6.15. DRAM Interface Characteristics
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
Test Conditions
VIL
Input Low Voltage
3
0.8
V
VIH
Input High Voltage
2.0
V
VOL
Output Low Voltage
3 to 18
0.4
V
IL = 1.6 mA
VOH
Output High Voltage
2.4
V
IL = *0.5 mA
tT
Output Transition Time
5
10
ns
CL = 15 pF
VOL(max) VOH(min)
3.6.15.1. DRAM Fast Mode Timing at fCLK = 20.25 MHz
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
Test Conditions
tPC
Page Mode Cycle Time
6
98.8
ns
DRAM:
tPC
>55
tCAS
CAS Pulse Width
60
ns
DRAM:
tCAS >25
tCP
CAS Precharge Time
10
ns
DRAM:
tCP
>10
tRP
RAS Precharge Time
5
90
ns
DRAM:
tRP
>80
tRSH
RAS Hold Time
5, 6
40
ns
DRAM:
tRSH >25
tCSH
CAS Hold Time
110
ns
DRAM:
tCSH > 100
tRCD
RAS to CAS Delay Time
45
ns
DRAM:
tRCD >25
tCRP
CAS to RAS Precharge Time
55
ns
DRAM:
tCRP >10
tASR
Row Address Setup Time
5, 7 to 18
55
ns
DRAM:
tASR >0
tRAH
Row Address Hold Time
15
ns
DRAM:
tRAH >15
tAR
Column Address Hold Time
105
ns
DRAM:
tAR
>75
tRAL
Column Address Lead Time
55
ns
DRAM:
tRAL >50
tASC
Column Address Setup Time
6, 7 to 18
5
ns
DRAM:
tASC >0
tCAH
Column Address Hold Time
60
ns
DRAM:
tCAH >20
tRRH
Read Command Hold Time
4, 5
80
ns
DRAM:
tRRH >0
tRCH
Read Command Hold Time
4, 6
50
ns
DRAM:
tRCH >0
tWCH
Write Command Hold Time
90
ns
DRAM:
tWCH >20
tWCS
Write Command Setup Time
30
ns
DRAM:
tWCS >0
tDOHR
DATA Output Hold Time RAS
3, 5
105
ns
DRAM:
tDHR >75
tDOS
DATA Output Setup Time
3, 6
0
ns
DRAM:
tDS
>0
tDOH
DATA Output Hold Time
60
ns
DRAM:
tDH
>20
tDIS
DATA Input Setup Time
20
ns
DRAM:
tCAC <25
tDIH
DATA Input Hold Time
0
ns
DRAM:
tOFF <30
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