參數(shù)資料
型號: TPS7350Y
廠商: Texas Instruments, Inc.
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Low-Dropout Voltage Regulators(帶延遲復(fù)位功能的低壓差穩(wěn)壓器)
中文描述: 低壓差穩(wěn)壓器(帶延遲復(fù)位功能的低壓差穩(wěn)壓器)
文件頁數(shù): 2/37頁
文件大小: 839K
代理商: TPS7350Y
TPS7301Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124D – JUNE 1995 – REVISED JANUARY 1997
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The RESET output of the TPS73xx is designed to initiate a reset in microcomputer and micro-processor
systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output
voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET output (open-drain NMOS) turns on, taking the RESET signal low. RESET stays low
for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out
begins. At the completion of the 200-ms delay, RESET goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance
is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35 mV
at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure 1).
Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains
constant, independent of output loading (typically 340
μ
A over the full range of output current, 0 mA to 500 mA).
These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN (enable) shuts down the regulator,
reducing the quiescent current to 0.5
μ
A maximum at T
J
= 25
°
C.
The TPS73xx is offered in 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2%
over line, load, and temperature ranges (3% for adjustable version). The TPS73xx family is available in PDIP
(8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2 mm.
Figure 1. Dropout Voltage Versus Output Current
0.1
0.05
0
0
0.05 0.1 0.15 0.2 0.25 0.3
IO – Output Current – A
D
0.15
0.2
0.25
0.35 0.4 0.45 0.5
TA = 25
°
C
TPS7348
TPS7350
TPS7333
Figure 2. Typical Application Configuration
TPS7333, TPS7348, TPS7350 (fixed-voltage options)
Capacitor selection is nontrivial. See application information
section for details.
SENSE
RESET
OUT
OUT
9
8
6
10
IN
IN
IN
EN
GND
3
2
1
20
15
14
13
VI
0.1
μ
F
To System
Reset
250 k
CSR = 1
VO
10
μ
F
+
TPS73xxPW
CO
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