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參數(shù)資料
| 型號(hào)： | TPS7333Y |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION |
| 中文描述： | 低技術(shù)，集成延遲復(fù)位功能降穩(wěn)壓器 |
| 文件頁數(shù)： | 33/43頁 |
| 文件大小： | 638K |
| 代理商： | TPS7333Y |
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TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
33
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
THERMAL INFORMATION
In response to system-miniaturization trends, integrated circuits are being offered in low-profile and fine-pitch
surface-mount packages. Implementation of many of today’s high-performance devices in these packages requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat
sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation
limits of a given component.
Three basic approaches for enhancing thermal performance are illustrated in this discussion:
Improving the power-dissipation capability of the PWB design
Improving the thermal coupling of the component to the PWB
Introducing airflow in the system
Figure 44 is an example of a thermally enhanced PWB layout for the 20-lead TSSOP package. This layout involves
adding copper on the PWB to conduct heat away from the device. The R
θ
JA
(thermal resistance, junction-to-ambient)
for this component/board system is illustrated in Figure 45. The family of curves illustrates the effect of increasing
the size of the copper-heat-sink surface area. The PWB is a standard FR4 board (L
×
W
×
H = 3.2 inch
×
3.2 inch
×
0.062 inch); the board traces and heat sink area are 1-oz (per square foot) copper.
Figure 46 shows the thermal resistance for the same system with the addition of a thermally-conductive compound
between the body of the TSSOP package and the PWB copper routed directly beneath the device. The thermal
conductivity for the compound used in this analysis is 0.815 W/m
×
°
C.
Using these figures to determine the system R
θ
JA
allows the maximum power-dissipation limit to be calculated with
the equation:
PD(max)
TJ(max)
RJA(system)
TA
Where
T
J(max)
is the maximum allowable junction temperature; 150
°
C absolute maximum and 125
°
C
maximum recommended operating temperature for specified operation.
This limit should then be applied to the internal power dissipated by the TPS73xx regulator. The equation for
calculating total internal power dissipation of the TPS73xx is:
PD(total)
VI
VO
IO
VI
IQ
Because the quiescent current of the TPS73xx family is very low, the second term is negligible, further simplifying
the equation to:
PD(total)
VI
VO
IO
For a 20-lead TSSOP/FR4 board system with thermally conductive compound between the board and the device
body, where T
A
= 55
°
C, airflow = 100 ft/min, and copper heat sink area = 1 cm
2
, the maximum power-dissipation limit
can be calculated. As indicated in Figure 46, the system R
θ
JA
is 94
°
C/W; therefore, the maximum power-dissipation
limit is:
PD(max)
TJ(max)
RJA(system)
TA
125 C
94 C W
55 C
745 mW
If the system implements a TPS7348 regulator where V
I
= 6 V and I
O
= 150 mA, the internal power dissipation is:
PD(total)
VI
VO
IO
(6
4.85)
0.150
173 mW
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| TPS73401DRVR | 功能描述:低壓差穩(wěn)壓器 - LDO Sgl Out,250mA,Adj,Lo Quies Crnt,Hi PSRR RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| TPS73401DRVT | 功能描述:低壓差穩(wěn)壓器 - LDO Sgl Out,250mA,Adj,Lo Quies Crnt,Hi PSRR RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
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