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參數(shù)資料
| 型號(hào)： | TPS65552ADGQRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 3 A BATTERY CHARGE CONTROLLER, PDSO10 |
| 封裝： | GREEN, POWERPAD, PLASTIC, MSOP-10 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 621K |
| 代理商： | TPS65552ADGQRG4 |
www.ti.com
PRODUCT
PREVIEW
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
DISSIPATION RATINGS
TPS65552A
SLVS567 – JULY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TARGET VOLTAGE at
TA
PACKAGE MARKING
PACKAGE
PART NUMBER
PRIMARY SIDE
-35
°C to 85°C
29
BKV
16-pin QFN
TPS65552ARGT
-35
°C to 85°C
29
BMA
10-pin MSOP
TPS65552ADGQ
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VCC
-0.6 V to 6 V
VSS
Supply voltage
VBAT
-0.6 V to 13 V
V(SW)
Switch terminal voltage
-0.6 V to 50 V
Switch current between SW and PGND, ISW
3 A
VI
Input voltage of CHG, I_PEAK, F_ON
-0.3 V to VCC
Tstg
Storage temperature
-40
°C to 150°C
TJ
Maximum junction temperature
125
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
MIN
NOM
MAX
UNIT
Supply voltage, VCC
4.5
5.5
V
VSS
Supply voltage, VBAT
1.8
12
V
V(SW)
Switch terminal voltage,
-0.3
45
V
Switch current between SW and PGND
2
A
Operating free-air temperature range
-35
85
°C
VIH
High-level digital input voltage at CHG and F_ON
2.4
V
VIL
Low-level digital input voltage at CHG and F_ON
0.6
V
POWER RATING
PACKAGE
RθJA
(1)
TA < 25°C
TA = 70°C
TA = 85°C
MSOP
49.08
°C/W
2.04 W
1.12 W
815 mW
QFN
47.40
°C/W
2.11 W
1.16 W
844 mW
(1)
The thermal resistance, RθJA, is based on a soldered PowerPAD on a 2S2P JEDEC board using thermal vias.
2
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