TPS62400-Q1, TPS62401-Q1
TPS62402-Q1, TPS62403-Q1
SLVSA67 – FEBRUARY 2010
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180° OUT-OF-PHASE OPERATION
In PWM Mode the converters operate with a 180° turn-on phase shift of the PMOS (high side) transistors. This
prevents the high-side switches of both converters from being turned on simultaneously, and therefore smooths
the input current. This feature reduces the surge current drawn from the supply.
SHORT-CIRCUIT PROTECTION
Both outputs are short-circuit protected with maximum output current = ILIMF(P-MOS and N-MOS). Once the
PMOS switch reaches its current limit, it is turned off and the NMOS switch is turned on. The PMOS only turns
on again, once the current in the NMOS decreases below the NMOS current limit.
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this
mode, the P and N-Channel MOSFETs are turned-off. The device continues its operation when the junction
temperature falls below the thermal shutdown hysteresis.
EasyScale: One-Pin Serial Interface for Dynamic Output Voltage Adjustment
General
EasyScale is a simple but very flexible one pin interface to configure the output voltage of both DC/DC
converters. The interface is based on a master – slave structure, where the master is typically a microcontroller
or application processor.
Figure 34 and
Table 3. give an overview of the protocol. The protocol consists of a
device specific address byte and a data byte. The device specific address byte is fixed to 4E hex. The data byte
consists of five bits for information, two address bits, and the RFA bit. RFA bit set to high indicates the Request
For Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly.
The advantage of EasyScale compared to other one pin interfaces is that its bit detection is in a large extent
independent from the bit transmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to
160kBit/sec. Furthermore, the interface is shared with the Mode/Data Pin and requires no additional pin.
Protocol
All bits are transmitted MSB first and LSB last.
Figure 35 shows the protocol without acknowledge request (bit
RFA = 0),
Figure 36 with acknowledge (bit RFA = 1) request.
Prior to both bytes, device address byte and data byte, a start condition needs to be applied. For this, the
Mode/Data pin need be pulled high for at least tStart before the bit transmission starts with the falling edge. In
case the Mode/Data line was already at high level (forced PWM Mode selection), no start condition need be
applied prior the device address byte.
The transmission of each byte needs to be closed with an End Of Stream condition for at least TEOS.
Addressable Registers
Three registers with a data content of 5 bits can be addressed. With 5 bit data content, 32 different values for
each register are available.
Table 1 shows the addressable registers to set the output voltage when DEF_1 pin
works as digital input. In this case, converter 1 has a related register for each DEF_1 Pin condition, and one
register for converter 2. With a high/low condition on pin DEF_1 (TPS62401) either the content of register
REG_DEF_1_high/REG_DEF1_low is selected. The output voltage of converter 1 is set according to the values
Table 2 shows the addressable registers if DEF_1 pin acts as analog input with external resistors connected. In
this case one register is available for each converter. The output voltage of converter 1 is set according to the
values in
Table 5. For converter 2, the available voltages are shown in
Table 6. To generate these output
voltages a precise internal resistor divider network is used, making external resistors unnecessary (less board
space), and provides higher output voltage accuracy. The Interface is activated if at least one of the converters is
enabled (EN1 or EN2 is high). After the startup-time tStart (170ms) the interface is ready for data reception.
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