參數(shù)資料
型號(hào)： TPS62000YEGT
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： 1.6 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, BGA12
封裝： DSBGA-12
文件頁(yè)數(shù)： 7/26頁(yè)
文件大?。?/td> 878K
代理商： TPS62000YEGT
INPUT CAPACITOR SELECTION
O
RMS
O(max)
I
V
I
= I
1
V
-
÷
è
(7)
The worst case RMS ripple current occurs at D = 0.5 and is calculated as:
O
RMS
I
=
2
LAYOUT CONSIDERATIONS
VIN
1
8
6
7
3
2
9
5
10
4
L1
EN
ILIM
SYNC
GND
FC
PG
PGND
FB
L
TPS62000
+
Co
VO
C3
Ci
VI
R3
R1
C(ff)
R2
+
PG
www.ti.com ........................................................................................................................................... SLVS294E – SEPTEMBER 2000 – REVISED AUGUST 2008
Table 3. Tested Capacitors
CAPACITOR VALUE
ESR/m
COMPONENT SUPPLIER
COMMENTS
10
F
50
Taiyo Yuden JMK316BJ106KL
Ceramic
47
F
100
Sanyo 6TPA47M
POSCAP
68
F
100
Spraque 594D686X0010C2T
Tantalum
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes.
The input capacitor should have a minimum value of 10
F and can be increased without any limit for better input
voltage filtering.
The input capacitor should be rated for the maximum input ripple current calculated as:
Ceramic capacitor show a good performance because of their low ESR value, and they are less sensitive against
voltage transients compared to tantalum capacitors.
Place the input capacitor as close as possible to the input pin of the IC for best performance.
As for all switching power supplies, the layout is an important step in the design especially at high peak currents
and switching frequencies. If the layout is not carefully done, the regulator might show stability problems as well
as EMI problems.
Therefore, use wide and short traces for the main current paths as indicted in bold in Figure 16. The input
capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. Place
the bypass capacitor, C3, as close as possible to the FC pin. The analog ground, GND, and the power ground,
PGND, need to be separated. Use a common ground node as shown in Figure 16 to minimize the effects of
ground noise.
Figure 16. Layout Diagram
Copyright 2000–2008, Texas Instruments Incorporated
15
相關(guān)PDF資料
PDF描述
TPS62000YEG 1.6 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, BGA12
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TPS62080DSG 0.002 A SWITCHING REGULATOR, PDSO8
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