參數(shù)資料
型號: TPS61131PWG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: 1.6 A BATTERY CHARGE CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PDSO16
封裝: GREEN, PLASTIC, TSSOP-16
文件頁數(shù): 11/29頁
文件大?。?/td> 861K
代理商: TPS61131PWG4
www.ti.com
Small Signal Stability
A
REG +
d
V
FB
+
10
(R3 ) R6)
R6
(1 ) i
w
1.6 ms)
(10)
Output Capacitor LDO
Layout Considerations
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
capacitance needs to be larger than calculated above to meet the total ripple requirements. The output capacitor
has to completely supply the load during the charging phase of the inductor. A reasonable value of the output
capacitance depends on the speed of the load transients and the load current during the load change. With the
calculated minimum value of 26
Fand load transient considerations the recommended output capacitance value
is in a 100
F range. For economical reasons this usually is a tantalum capacitor. Because of this the control
loop has been optimized for using output capacitors with an ESR of above 30 m
. The minimum value for the
output capacitor is 22
F.
When using output capacitors with lower ESR, like ceramics, it is recommended to use the adjustable voltage
version. The missing ESR can be easily compensated there in the feedback divider. Typically a capacitor in the
range of 10 pF in parallel with R3 helps to obtain small signal stability, with the lowest ESR output capacitors.
For more detailed analysis the small signal transfer function of the error amplifier and regulator, which is given in
Equation 10, can be used.
To ensure stable output regulation, it is required to use an output capacitor at the LDO output. Ceramic
capacitors in the range from 1
F up to 4.7 F are recommend. At 4.7 F and above it is recommended to use
standard ESR tantalum. There is no maximum capacitance value.
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the
control ground, it is recommended to use short traces as well, separated from the power ground traces. This
avoids ground shift problems, which can occur due to superimposition of power ground current and control
ground current.
Copyright 2002–2008, Texas Instruments Incorporated
19
Product Folder Link(s): TPS61130 TPS61131 TPS61132
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