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參數(shù)資料
| 型號： | TPS61045DRBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.45 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | 3 X 3 MM, GREEN, PLASTIC, SON-8 |
| 文件頁數(shù)： | 21/21頁 |
| 文件大?。?/td> | 582K |
| 代理商： | TPS61045DRBR |
V
O(DO) +
V
ref
26–1
td1
t(DWN)
td1
t(OFF)
Device Enabled
Device Disabled
High
Low
EN
td1
t(UP)
www.ti.com
SLVS440B – JANUARY 2003 – REVISED MARCH 2009
DAC OUTPUT (DO)
The TPS61045 allows digital adjustment of the output voltage using the digital CTRL interface as described in
the next section. The DAC output pin (DO) drives an external resistor (R3) connected to the external feedback
divider. The DO output has a typical output voltage range from 0 V to Vref (1.233V). If the DO output voltage is
set to 0 V, the external resistor (R3) is more or less in parallel to the lower feedback resistor (R2) giving the
highest output voltage. Programming the DO output to Vref gives the lowest output voltage. Internally, a 6-bit DAC
is used with 64-steps and 0 as the first step. This gives a typical voltage step of 19.6 mV which is calculated as:
See the SETTING THE OUTPUT VOLTAGE section for further information.
After start-up, when the CTRL pin is pulled high, the DO output voltage is set to its center voltage which is the
32nd step of typically V(DO) = 607mV.
DIGITAL INTERFACE (CTRL)
When the CTRL pin is pulled high the device starts up with softstart and the DAC output voltage (DO) sets to its
center voltage with a typical output voltage of 607 mV.
The output voltage can be programmed by pulling the CTRL pin low for a certain period of time. Depending on
this time period the internal DAC voltage increases or decreases one digital step, as outlined in Table 2 and
Figure 16. Programming the DAC output V(DO) to 0 V places R3 in parallel to R2, which gives the maximum
output voltage. If the DAC is programmed to its maximum output voltage equal to the internal reference voltage,
typically V(DO) = 1.233 V, then the output has its minimum output voltage.
Table 2. Timing Table
DAC OUTPUT DO
TIME
LOGIC LEVEL
Increase one step
tUP = 1 ms to 60 ms
Low
Decrease one step
tDWN = 140 ms to 240 ms
Low
Shutdown
tOFF ≥ 560 ms
Low
Delay between steps
td1 = 1 ms
High
Figure 16. CTRL Timing Diagram
UNDERVOLTAGE LOCKOUT
An undervoltage lockout feature prevents misoperation of the device at input voltages below 1.5 V (typ). As long
as the input voltage is below the undervoltage threshold the device remains off, with the input switch (Q1) and
the main switch (Q2) open.
THERMAL SHUTDOWN
An internal thermal shutdown is implemented in the TPS61045 that shuts down the device if the typical junction
temperature of 160°C is exceeded. If the device is in thermal shutdown mode, the input switch (Q1) and the main
switch (Q2) are open.
Copyright 2003–2009, Texas Instruments Incorporated
9
Product Folder Link(s): TPS61045
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