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參數資料
| 型號： | TPS561000PWP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1.4 A SWITCHING CONTROLLER, PDSO28 |
| 封裝： | PLASTIC, TSSOP-28 |
| 文件頁數： | 22/27頁 |
| 文件大小： | 370K |
| 代理商： | TPS561000PWP |
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TPS56100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR 5-V INPUT SYSTEMS
SLVS201A – JUNE 1999 – REVISED JULY 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
ANAGND
7
I
Analog ground
BIAS
9
I
Analog BIAS pin. This terminal must be connected to 5-V supply voltage. A 1-
F ceramic capacitor should be
connected from BIAS to ANAGND.
BOOT
16
I
Bootstrap. Connect a 1-
F low-ESR capacitor from BOOT to BOOTLO.
BOOTLO
18
I
Bootstrap low. Connect BOOTLO to the junction of the high-side and low-side FETs for floating drive
configuration. Connect BOOTLO to PGND for ground reference drive configuration.
DRV
14
I
Drive bias for the FET drivers. This terminal must be connected to 5-V supply voltage. A 1-
F ceramic capacitor
should be connected from DRV to DRVGND.
DRVGND
12
I
Drive ground. Ground for FET drivers. Connect to FET PWRGND.
HIGHDR
17
O
High drive. Output drive to high-side power switching FETs
HISENSE
19
I
High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs; for
optional resistor sensing scheme, connect to power supply side of current-sense resistor placed in series with
high-side FET drain.
INHIBIT
22
I
Disables the drive signals to the MOSFET drivers.
IOUT
1
O
Current out. Output voltage on this pin is proportional to the load current as measured across the Rds(on) of the
high-side FETs. The voltage on this pin equals 2
×Rds(on)×IOUT. In applications where very accurate current
sensing is required, a sense resistor should be connected between the input supply and the drain of the high-side
FETs.
IOUTLO
21
O
Current sense low output. This is the voltage on the LOSENSE pin when the high-side FETs are on. A ceramic
capacitor should be connected from IOUTLO to HISENSE to hold the sensed voltage while the high-side FETs
are off. Capacitance range should be between 0.033
F and 0.1 F.
LODRV
10
I
Low drive enable. Normally tied to 5 V. To activate the low-side FETs as a crowbar, pull LODRV low.
LOHIB
11
I
Low side inhibit. Connect to the junction of the high and low side FETs to control the anti-cross-conduction and
eliminate shoot-through current. Disabled when configured in crowbar mode.
LOSENSE
20
I
Low current sense. For current sensing across high-side FETs, connect to the source of the high-side FETs; for
optional resistor sensing scheme, connect to high-side FET drain side of current-sense resistor placed in series
with high-side FET drain.
LOWDR
13
O
Low drive. Output drive to synchronous rectifier FETs
NC
2
Not connected
OCP
3
I
Over current protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND.
PWRGD
28
O
Power good. Power Good signal goes high when output voltage is within 7% of voltage set by VID pins.
Open-drain output.
SLOWST
8
O
Slow Start (soft start). A capacitor from SLOWST to ANAGND sets the slowstart time.
Slowstart current = IVREFB/5
VCC
15
I
5-V supply. A 1-
F ceramic capacitor should be connected from VCC to DRVGND.
VHYST
4
I
HYSTERESIS set pin. The hysteresis is set with a resistor divider from VREFB to ANAGND.
The hysteresis window = 2
× (VREFB – VHYST)
VP0
27
I
Voltage programming input 0
VP1
26
I
Voltage programming input 1
VP2
25
I
Voltage programming input 2
VP3
24
I
Voltage programming input 3
VP4
23
I
Voltage programming input 4. Digital inputs that set the output voltage of the converter. The code pattern for
setting the output voltage is located in Table 1. Internally pulled up to 5 V.
VREFB
5
O
Buffered reference voltage from VP network
VSENSE
6
I
Voltage sense Input. To be connected to converter output voltage bus to sense and control output voltage. It is
recommended that an RC low pass filter be connected at this pin to filter noise.
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