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VBIAS Regulator (VBIAS)
Oscillator and PWM Ramp
SWITCHING FREQUENCY (MHz) =
51 k
R( ) + 4.7 k
W
(4)
Voltage Reference
Error Amplifier
The high performance, wide bandwidth, voltage error
amplifier sets the TPS54377 apart from most dc/dc
converters. The user is given the flexibility to use a
wide range of output L and C filter components to suit
the particular application needs. Type 2 or type 3
compensation
can
be
employed
compensation components.
PWM Control
TPS54377
SLVS779–SEPTEMBER 2007
The VBIAS regulator provides internal analog and
digital blocks with a stable supply voltage over
variations in junction temperature and input voltage. A
high quality, low-ESR, ceramic bypass capacitor is
required on the VBIAS pin. X7R or X5R grade
dielectrics are recommended because their values
are more stable over temperature. The bypass
capacitor should be placed close to the VBIAS pin
and returned to AGND. External loading on VBIAS is
allowed, with the caution that internal circuits require
a minimum VBIAS of 2.70 V, and external loads on
VBIAS with ac or digital switching noise may degrade
performance. The VBIAS pin may be useful as a
reference voltage for external circuits.
The oscillator frequency can be set to internally fixed
values of 350 kHz or 550 kHz using the SYNC pin as
a static digital input. If a different frequency of
operation is required for the application, the oscillator
frequency can be externally adjusted from 280 kHz to
1600 kHz by connecting a resistor to the RT pin to
ground and floating the SYNC pin. The switching
frequency is approximated by the following equation,
where R is the resistance from RT to AGND:
External
possible over the frequency range of 330 kHz to 1600
kHz by driving a synchronization signal into SYNC
and connecting a resistor from RT to AGND. Choose
an RT resistor that sets the free-running frequency to
80%
of
the
synchronization
summarizes the frequency selection configurations.
synchronization
of
the
PWM
ramp
is
The voltage reference system produces a precise V
ref
signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap
and scaling circuits are trimmed to produce 0.891 V
at the output of the error amplifier, with the amplifier
connected as a voltage follower. The trim procedure
adds
to
the
high
precision
TPS54377, since it cancels offset errors in the scale
and error amplifier circuits.
signal.
Table
1
regulation
of
the
Table 1. Summary of the Frequency Selection Configurations
SWITCHING FREQUENCY
350 kHz, internally set
550 kHz, internally set
Externally set 280 kHz to 1600 kHz
Externally synchronized frequency
SYNC PIN
RT PIN
Float or AGND
≥
2.5 V
Float
Synchronization signal
Float
Float
R = 27.4 k to 180 k
R = RT value for 80% of external synchronization frequency
to its valley voltage. When the ramp begins to charge
back up, the low-side FET turns off and high-side
FET turns on. As the PWM ramp voltage exceeds the
error amplifier output voltage, the PWM comparator
resets the latch, thus turning off the high-side FET
and turning on the low-side FET. The low-side FET
remains on until the next oscillator pulse discharges
the PWM ramp.
using
external
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or
above the PWM peak voltage. If the error amplifier is
high, the PWM latch is never reset and the high-side
FET remains on until the oscillator pulse signals the
control logic to turn off the high-side FET and turns
on the low-side FET. The device operates at its
maximum duty cycle until the output voltage rises to
the
regulation
set-point,
approximately the same voltage as V
ref
. If the error
amplifier output is low, the pwm latch is continually
reset and the high-side FET does not turn on. The
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the
control logic includes the PWM comparator, OR gate,
PWM latch, and portions of the adaptive dead-time
and control logic block. During steady-state operation
below
the
current
limit
comparator
output
and
alternately reset and set the PWM latch. Once the
PWM latch is set, the low-side FET remains on for a
minimum duration set by the oscillator pulse duration.
During this period, the PWM ramp discharges rapidly
threshold,
oscillator
the
pulse
PWM
train
setting
VSENSE
to
Copyright 2007, Texas Instruments Incorporated
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TPS54377