參數(shù)資料
型號(hào): TPS54327DDAR
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: 5.7 A SWITCHING REGULATOR, 700 kHz SWITCHING FREQ-MAX, PDSO8
封裝: GREEN, PLASTIC, MS-012BA, SOP-8
文件頁數(shù): 3/18頁
文件大?。?/td> 399K
代理商: TPS54327DDAR
V
= 0.765 x
OUT
R1
1 +
R2
÷
÷
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è
F
=
P
OUT
1
2
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x C
p
www.ti.com
SLVSAG1 – NOVEMBER 2010
DESIGN GUIDE
Step By Step Design Procedure
To begin the design process, you must know a few application parameters:
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
Figure 13. Shows the schematic diagram for this design example.
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable.
(2)
Output Filter Selection
The output filter used with the TPS54327 is an LC circuit. This LC filter has double pole at:
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54327. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a -40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that
reduces the gain roll off to -20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1
Copyright 2010, Texas Instruments Incorporated
11
Product Folder Link(s): TPS54327
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