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參數(shù)資料
| 型號： | TPS535G4 |
| 英文描述： | PHOTOVOLTAIC CELL FOR THERMOPILE DETECTION |
| 中文描述： | 光伏電池的熱電堆檢測 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 231K |
| 代理商： | TPS535G4 |
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description
reference/voltage identification
The reference /voltage programming (VP) section consists of a temperature-compensated, bandgap reference
and a 5-bit voltage selection network. The five VID pins are inputs to the VID selection network and are TTL
compatible inputs that are internally pulled up to V
CC
with pullup resistors. The internal reference voltage can
be programmed from 0.925 V to 2 V with the VID pins. The VID codes are listed in Table 1. The output voltage
of the VP network, V
ref
, is within
±
1.5% of the nominal setting. The
±
1.5% tolerance is over the full VP range
of 0.925 V to 2 V, and includes a junction temperature range of 0
°
C to 125
°
C, and a V
CC
range of 4.5 V to 5.5
V. The output of the reference/VP network is indirectly brought out through a buffer to the VREFB pin. The
voltage on this pin will be within
±
5 mV of V
ref
. It is not recommended to drive loads with VREFB, other than
setting the hysteresis of the hysteretic comparator, because the current drawn from VREFB sets the charging
current for the slowstart capacitor. Refer to the slowstart section for additional information.
dynamic VID change
Dynamic VID change controls the rate of change of the programmed VID to allow transitioning within 100
μ
s,
while controlling the dv/dt to avoid large input surge currents. VID could change with any input voltage, output
voltage, or output current. A new change is ignored until the current transition is finished. Program the transition
by adding a capacitor from DT_SET to ANAGND.
C
DT_SET
It
t
VREF
14
μ
A
t
VREF2
VREF1
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by two external resistors and is centered around VREFB. The two external resistors form a resistor divider
from VREFB to ANAGND, and the divided down voltage connects to the VHYST terminal. The hysteresis of the
comparator will be equal to twice the voltage that is across the VREFB and VHYST pins. The maximum
hysteresis setting is 60 mV.
ramp generator
The ramp generator circuit is partially composed of the PSM circuit. An external resistor from PH to
VSENSE_CORE superimposes a ramp (proportional to V
I
and V
O
) onto the feedback voltage. This allows
increasing the operating frequency, and reduces frequency dependance on the output filter values. A capacitor
can be used to provide ac-coupling. Also, connecting a resistor from V
I
to VSENSE_CORE allows feed forward
to counteract any dc offsets due to the ramp generator or propagation delays limiting duty cycle.
power saving mode/latch
The power saving mode circuit reduces the operating frequency of the ripple regulator during light load. This
helps boost the efficiency during light loads by reducing the switching losses. Care should be taken to not allow
rms current losses to exceed the switching losses. A 2
-
bit binary weighted resistor ramp circuit allows setting
four operating frequencies.
The PSM/LATCH terminal allows disabling of the fault latch (see Table 2). This allows the user to troubleshoot
or implement an external protection circuit.
P
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