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參數(shù)資料
| 型號： | TPS2148IDGNR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 4/18頁 |
| 文件大小： | 251K |
| 代理商： | TPS2148IDGNR |
TPS2148
TPS2158
SLVS373
–
AUGUST 2001
4
www.ti.com
electrical characteristics over recommended operating junction-temperature range,
2.9 V
≤
V
I(VIN/SWIN1)
≤
5.5 V, T
J
=
–
40
°
C to 100
°
C (unless otherwise noted)
timing parameters, power switches
PARAMETER
TEST CONDITIONS
MIN
0.5
TYP
MAX
UNIT
ton
Turnon time OUTx switch (see Note 1)
Turnon time, OUTx switch, (see Note 1)
CL = 100
μ
F
CL = 1
μ
F
CL = 100
μ
F
CL = 1
μ
F
CL = 100
μ
F
CL = 1
μ
F
CL = 100
μ
F
CL = 1
μ
F
RL= 33
RL = 33
6
0.1
3
tff
toff
Turnoff time OUTx switch (see Note 1)
Turnoff time, OUTx switch (see Note 1)
RL= 33
RL = 33
5.5
10
ms
0.05
2
tr
Rise time OUTx switch (see Note 1)
Rise time, OUTx switch (see Note 1)
RL= 33
RL = 33
0.5
5
0.1
2
tf
Fall time OUTx switch (see Note 1)
Fall time, OUTx switch (see Note 1)
RL= 33
RL = 33
5.5
0.05
9
1.2
NOTE 1. Specified by design, not tested in production.
undervoltage lockout at VIN/SWIN1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UVLO Threshold
2.2
2.85
V
Hysteresis (see Note 1)
260
mV
μ
s
Deglitch (see Note 1)
50
NOTE 1. Specified by design, not tested in production.
undervoltage lockout at switch 2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UVLO Threshold
2.2
2.85
V
Hysteresis (see Note 1)
260
mV
μ
s
Deglitch (see Note 1)
50
NOTE 1. Specified by design, not tested in production.
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