參數(shù)資料
型號(hào)： TP3067B
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
中文描述： 整體式串行接口的PCM編解碼器和過濾器
文件頁(yè)數(shù)： 7/21頁(yè)
文件大小： 300K
代理商： TP3067B
TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCMCODEC AND FILTER
SCTS031D – MAY 1990 –REVISED JULY 1996
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fclock(M)
Frequency of master clock
MCLX
and
MCLKR
Depends on the device used and
BCLKX/CLKSEL
1.536
1.544
2.048
MHz
fclock(B)
Frequency of bit clock, transmit
BCLKX
64
2.048
MHz
tr1
Rise time of master clock
MCLKX
and
MCLKR
Measured from 20% to 80%
50
ns
tf1
Fall time of master clock
MCLKX
and
MCLKR
Measured from 20% to 80%
50
ns
tr2
tf2
tw1
tw2
Rise time of bit clock, transmit
BCLKX
Measured from 20% to 80%
50
ns
Fall time of bit clock, transmit
BCLKX
Measured from 20% to 80%
50
ns
Pulse duration, MCLKX and MCLKR high
160
ns
Pulse duration, MCLKX and MCLKR low
160
ns
tsu1
Setup time, BCLKX high (and FSX in long-frame
sync mode) before MCLKX
↓
Pulse duration, BCLKX and BCLKR high
First bit clock after the leading edge
of FSX
100
ns
tw3
tw4
VIH = 2.2 V
VIL = 0.6 V
160
ns
Pulse duration, BCLKX and BCLKR low
160
ns
th1
Hold time, frame sync low after bit clock low (long
frame only)
Hold time, BCLKX high after frame sync
↑
(short
frame only)
Setup time, frame sync high before bit clock
↓
(long
frame only)
0
ns
th2
0
ns
tsu2
80
ns
td1
td2
Delay time, BCLKX high to data valid
Load = 150 pF plus 2 LSTTL loads
0
140
ns
Delay time, BCLKX high to TSX low
Load = 150 pF plus 2 LSTTL loads
140
ns
td3
Delay time, BCLKX (or 8 clock FSX in long frame
only) low to data output disabled
50
165
ns
td4
Delay time, FSX or BCLKX high to data valid (long
frame only)
Setup time, DR valid before BCLKR
↓
Hold time, DR valid after BCLKR or BCLKX
↓
Setup time, FSR or FSX high before BCLKR or
BCLKX
↓
Hold time, FSX or FSR high after BCLKX or
BCLKR
↓
CL = 0 pF to 150 pF
20
165
ns
tsu3
th3
50
ns
50
ns
tsu4
Short-frame sync pulse (1- or 2-bit
clock periods long) (see Note 3)
50
ns
th4
Short-frame sync pulse (1- or 2-bit
clock periods long) (see Note 3)
100
ns
th5
Hold time, frame sync high after bit clock
↓
Long-frame sync pulse (from 3- to
8-bit clock periods long)
100
ns
tw5
All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25
°
C.
Nominal input value for an LSTTL load is 18 k
.
NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high.
Pulse duration of the frame sync pulse (low level)
64 kbps operating mode
160
ns
相關(guān)PDF資料
PDF描述
TP13064B MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
TP13064BDW MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
TP13064BN MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
TP13067B MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
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TP3067J 制造商:Texas Instruments 功能描述:
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