參數(shù)資料
型號(hào)： TP13067B
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
中文描述： 整體式串行接口的PCM編解碼器和過濾器
文件頁(yè)數(shù)： 15/21頁(yè)
文件大?。?/td> 300K
代理商： TP13067B
TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCMCODEC AND FILTER
SCTS031D – MAY 1990 –REVISED JULY 1996
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPALS OF OPERATION
VCC
DGND
VBB
Figure 3. Diode Configuration for Latch-Up Protection Circuitry
internal sequencing
Power-on reset circuitry initializes the TP3064B, TP3067B, TP13064B, and TP13067B devices when power
is first applied, placing it into the power-down mode. DX and VFRO outputs go into high-impedance states and
all nonessential circuitry is disabled. A low level or clock applied to MCLKR/PDN powers up the device and
activates all circuits. DX, a 3-state PCM data output, remains in the high-impedance state until the arrival of the
second FSX pulse.
power supplies
All ground connections to each device should meet at a common point as close as possible to ANLG–GND. This
minimizes the interaction of ground return currents flowing through a common bus impedance. V
CC
and V
BB
supplies should be decoupled by connecting 0.1-
μ
F decoupling capacitors between each power rail and this
common point. These bypass capacitors must be connected as close as possible to V
CC
and V
BB
.
For best performance, the ground point of each codec/filter on a card should be connected to a common card
ground in star formation rather than through a ground bus. This common ground point should be decoupled to
V
CC
and V
BB
with 10-
μ
F capacitors.
synchronous operation
For synchronous operation, a clock is applied to MCLKX. MCLKR/PDN is used as a power-down control. A logic
0 applied to MCLKR powers-up the device and a high level powers it down. In either case, MCLKX is selected
as the master clock for both receive and transmit direction. BCLKX must also have a bit clock applied to it. The
selection of the proper internal divider for a master-clock frequency of 1.536 MHz, 1.544 MHz, or 2.048 MHz
can be done using BCLKR/CLKSEL. The device automatically compensates for the 193rd clock pulse of each
frame.
A fixed level on BCLKR/CLKSEL selects BCLKX as the bit clock for both the transmit and receive directions.
Table 1 indicates the frequencies of operation that can be selected depending on the state of BCLKR/CLKSEL.
In the synchronous mode, BCLKX may be in the range from 64 kHz to 2.048 MHz but must be synchronous
with MCLKX.
The encoding cycle begins with each FSX pulse, and the PCM data from the previous cycle is shifted out of the
enabled DX output on the rising edge of BCLKX. After eight-bit clock periods, the 3-state DX output is returned
to the high-impedance state. With an FSR pulse, PCM data is latched via DR on the falling edge of BCLKX (or
BCLKR, if running). FSX and FSR must be synchronous with MCLKX and MCLKR.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TP13067BDW 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TP13067BJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law CODEC
TP13067BN 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TP130K 功能描述:鉗型萬用表及配件 AIR/GAS K TYPE PROBE RoHS:否 制造商:Fluke 準(zhǔn)確性:2 % 測(cè)距:400 A
TP130KA 功能描述:測(cè)試探頭 AIR/GAS PROBE K TYPE RoHS:否 制造商:Teledyne LeCroy 設(shè)備類型:Passive Probes 帶寬:500 MHz 尖端類型: 長(zhǎng)度:1.3 mm 顏色:Black 電壓額定值: 電流額定值:
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