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參數(shù)資料
| 型號： | TP13067ADW |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| 中文描述： | 整體式串行接口的PCM編解碼器和過濾器 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大小： | 283K |
| 代理商： | TP13067ADW |
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCMCODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
asynchronous operation
For asynchronous operation, separate transmit and receive clocks can be applied. MCLKX and MCLKR must
be 2.048 MHz for the TP3064A and TP13064A, 1.536 MHz or 1.544 MHz for the TP3067A and TP13067A and
need not be synchronous. However, for best performance, MCLKR should be synchronous with MCLKX. This
is easily achieved by applying only static logic levels to MCLKR/PDN. This connects MCLKX to all internal
MCLKR functions. For 1.544-MHz operation, the device compensates for the 193rd clock pulse of each frame.
Each encoding cycle is started with FSX, and FSX must be synchronous with MCLKX and BCLKX. Each
decoding cycle is started with FSR, and FSR must be synchronous with BCLKR. The logic levels shown in
Table 1 are not valid in the asynchronous mode. BCLKX and BCLKR can operate from 64 kHz to 2.048 MHz.
short-frame sync operation
The device can operate with either a short- or a long-frame sync pulse. On power up, the device automatically
goes into the short-frame mode where both FSX and FSR must be one bit-clock period long with timing
relationships specified in Figure 1. With FSX high during a falling edge of BCKLX, the next rising edge of BCLKX
enables the 3-state output buffer, DX, which outputs the sign bit. The remaining seven bits are clocked out on
the following seven rising edges, and the next falling edge disables DX. With FSR high during a falling edge
of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following
seven falling edges latch in the remaining bits. The short-frame sync pulse can be utilized in either the
synchronous or asynchronous mode.
long-frame sync operation
Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing
relationships, as shown in Figure 2. Using the transmit frame sync (FSX), the device detects whether a short-
or long-frame sync pulse is being used. For 64-kHz operation, the frame sync pulse must be kept low for a
minimum of 160 ns. The rising edge of FSX or BCLKX, which ever occurs later, enables the DX 3-state output
buffer. The first bit clocked out is the sign bit. The next seven rising edges of BCLKX edges clock out the
remaining seven bits. The falling edge of BCLKX following the eighth rising edge or FSX going low, whichever
occurs later, disables DX. A rising edge on FSR, the receive frame sync pulse, causes the PCM data at DR to
be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). The long-frame sync
pulse may be used in either the synchronous or asynchronous mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TP3067AN | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3064A | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3064ADW | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3064AN | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3067A | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP13067AJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law CODEC |
| TP13067AN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP13067B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP13067BDW | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13067BJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law CODEC |
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