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參數(shù)資料
| 型號： | TP13054A |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | Combination Codec/Filter(單片，串行接口，組合脈沖編碼譯碼器和濾波器) |
| 中文描述： | 組合編解碼器/濾波器（單片，串行接口，組合脈沖編碼譯碼器和濾波器） |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 361K |
| 代理商： | TP13054A |
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
ANLG GND
BCLKR/CLKSEL
2
7
Analog ground. All signals are referenced to ANLG GND.
The bit clock that shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternately,
BCLKR/CLKSEL can be a logic input that selects either 1.536 MHz/1.544 MHz or 2.048 MHz for the master clock in
the synchronous mode. BCLKX is used for both transmit and receive directions (see Table 1).
BCLKX
10
The bit clock that shifts out the PCM data on DX. May vary from 64 kHz to 2.048 MHz, but must be synchronous with
MCLKX.
DR
DX
FSR
6
Receive data input. PCM data is shifted into DR following the FSR leading edge.
The 3-state PCM data output that is enabled by FSX.
Receive-frame sync pulse input that enables BCLKR to shift PCM data in DR. FSR is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).
11
5
FSX
12
Transmit-frame sync pulse that enables BCLKX to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).
GSX
MCLKR/PDN
14
8
Analog output of the transmit input amplifier. GSX is used to externally set gain.
Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MCLKX, but should
be synchronous with MCLKX for best performance. When MCLKR is connected continuously low, MCLKX is selected
for all internal timing. When MCLKR is connected continuously high, the device is powered down.
MCLKX
TSX
VBB
VCC
VFRO
VFXI+
VFXI–
9
Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MCLKR
Open-drain output that pulses low during the encoder time slot
Negative power supply. VBB = –5 V
±
5%
Positive power supply. VCC = 5 V
±
5%
Analog output of the receive filter
Noninverting input of the transmit input amplifier
Inverting input of the transmit input amplifier
13
1
4
3
16
15
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| TP13067AN | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3067ADW | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP13067ADW | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3067AN | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP13054ADW | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13054ADWR | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13054AJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC |
| TP13054AN | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13054B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
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