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參數(shù)資料
| 型號(hào)： | TOOLSTICK340PP |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 249/276頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | ADAPTER PROGRAM TOOLSTICK F340 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ToolStick |
| 類型： | 微控制器編程器 |
| 適用于相關(guān)產(chǎn)品： | C8051F340/341/344/345 |
| 所含物品： | 2 個(gè)板和 USB 連接線纜 |
| 產(chǎn)品目錄頁(yè)面： | 626 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | 336-1303-ND - IC 8051 MCU FLASH 32K 48TQFP 336-1302-ND - IC 8051 MCU FLASH 64K 48TQFP 336-1299-ND - IC 8051 MCU FLASH 32K 48TQFP 336-1298-ND - IC 8051 MCU FLASH 64K 48TQFP |
| 其它名稱： | 336-1452 |
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C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
74
Rev. 1.3
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that for execution time.
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2). Note that the re-program-
mable Flash can also be read and changed a single byte at a time by the application software using the
MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data stor-
age as well as updating program code under software control.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with-
out occupying package pins. C2 details can be found in Section “23. C2 Interface” on page 271.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including editor, debugger, and programmer. The
IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient
in-system device programming and debugging. An 8051 assembler, linker and evaluation ‘C’ compiler are
included in the Development Kit. Many third party macro assemblers and C compilers are also available,
which can be used directly with the IDE.
9.1.
Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51 instruc-
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51 counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
9.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take two fewer clock
cycles to complete when the branch is not taken as opposed to when the branch is taken. Table 9.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
Clocks to Execute
1
2
2/4
3
3/5
4
5
4/6
6
8
Number of Instructions
26
50
5
10
7
5
2
1
2
1
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