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參數(shù)資料
| 型號(hào)： | TN80C188EBxx |
| 廠商： | Intel Corp. |
| 英文描述： | 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS |
| 中文描述： | 16位高集成嵌入式處理器 |
| 文件頁數(shù)： | 27/59頁 |
| 文件大?。?/td> | 779K |
| 代理商： | TN80C188EBXX |
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80C186EB/80C188EB, 80L186EB/80L188EB
I
CC
VERSUS FREQUENCY AND VOLTAGE
The current (I
CC
) consumption of the processor is
essentially composed of two components; I
PD
and
I
CCS
.
I
PD
is the
quiescent
current that represents internal
device leakage, and is measured with all inputs or
floating outputs at GND or V
CC
(no clock applied to
the device). I
PD
is equal to the Powerdown current
and is typically less than 50
m
A.
I
CCS
is the
switching
current used to charge and
discharge parasitic device capacitance when chang-
ing logic levels. Since I
CCS
is typically much greater
than I
PD
, I
PD
can often be ignored when calculating
I
CC
.
I
CCS
is related to the voltage and frequency at which
the device is operating. It is given by the formula:
Power
e
V
c
I
e
V
2
c
C
DEV
c
f
...
I
e
I
CC
e
I
CCS
e
V
c
C
DEV
c
f
Where: V
e
Device operating voltage (V
CC
)
C
DEV
e
Device capacitance
f
e
Device operating frequency
I
CCS
e
I
CC
e
Device current
Measuring C
DEV
on a device like the 80C186EB
would be difficult. Instead, C
DEV
is calculated using
the above formula by measuring I
CC
at a known V
CC
and frequency (see Table 11). Using this C
DEV
val-
ue, I
CC
can be calculated at any voltage and fre-
quency within the specified operating range.
EXAMPLE: Calculate the typical I
CC
when operating
at 10 MHz, 4.8V.
I
CC
e
I
CCS
e
4.8
c
0.583
c
10
&
28 mA
PDTMR PIN DELAY CALCULATION
The PDTMR pin provides a delay between the as-
sertion of NMI and the enabling of the internal
clocks when exiting Powerdown. A delay is required
only when using the on-chip oscillator to allow the
crystal or resonator circuit time to stabilize.
NOTE:
The PDTMR pin function does not apply when
RESIN is asserted (i.e., a device reset during Pow-
erdown is similar to a cold reset and RESIN must
remain active until after the oscillator has stabi-
lized).
To calculate the value of capacitor required to pro-
vide a desired delay, use the equation:
440
c
t
e
C
PD
(5V, 25
§
C)
Where: t
e
desired delay in
seconds
C
PD
e
capacitive load on PDTMR in
mi-
crofarads
EXAMPLE: To get a delay of 300
m
s, a capacitor
value of C
PD
e
440
c
(300
c
10
b
6
)
e
0.132
m
F is
required. Round up to standard (available) capaci-
tive values.
NOTE:
The above equation applies to delay times greater
than 10
m
s and will compute the
TYPICAL
capaci-
tance needed to achieve the desired delay. A delay
variance of
a
50% or
b
25% can occur due to
temperature,
voltage,
and
tremes. In general, higher V
CC
and/or lower tem-
perature will decrease delay time, while lower V
CC
and/or higher temperature will increase delay time.
device
process
ex-
Table 11. Device Capacitance (C
DEV
) Values
Parameter
Typ
Max
Units
Notes
C
DEV
(Device in Reset)
0.583
1.02
mA/V
*
MHz
1, 2
C
DEV
(Device in Idle)
1. Max C
DEV
is calculated at
b
40
§
C, all floating outputs driven to V
CC
or GND, and all
outputs loaded to 50 pF (including CLKOUT and OSCOUT).
2. Typical C
DEV
is calculated at 25
§
C with all outputs loaded to 50 pF except CLKOUT and
OSCOUT, which are not loaded.
0.408
0.682
mA/V
*
MHz
1, 2
27
27
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TN80C188XL10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| TN80C188XL12 | 功能描述:IC MPU 16-BIT 5V 12MHZ 68-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| TN80C188XL-16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor |
| TN80C188XL20 | 功能描述:IC MPU 16-BIT 5V 20MHZ 68-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| TN80C188XL25 | 制造商:INNOVASIC 制造商全稱:INNOVASIC 功能描述:16-Bit Microcontroller |
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