參數(shù)資料
型號(hào)： TN80C186EB13
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
中文描述： 16-BIT, 13 MHz, MICROPROCESSOR, PQCC84
封裝： PLASTIC, LCC-84
文件頁(yè)數(shù)： 12/59頁(yè)
文件大小： 779K
代理商： TN80C186EB13
80C186EB/80C188EB, 80L186EB/80L188EB
Table 3. Pin Descriptions
(Continued)
Pin
Name
Pin
Type
Input
Type
Output
States
Description
DT/R
O
D
H(Z)
R(Z)
P(X)
Data Transmit/Receive
output controls the direction of a
bi-directional buffer in a buffered system. DT/R is only
available for the PLCC package.
LOCK
O
D
H(Z)
R(WH)
P(1)
LOCK
output indicates that the bus cycle in progress is not
to be interrupted. The processor will not service other bus
requests (such as HOLD) while LOCK is active. This pin is
configured as a weakly held high input while RESIN is
active and must not be driven low.
HOLD
I
A(L)
D
HOLD
request input to signal that an external bus master
wishes to gain control of the local bus. The processor will
relinquish control of the local bus between instruction
boundaries not conditioned by a LOCK prefix.
HLDA
O
D
H(1)
R(0)
P(0)
HoLD Acknowledge
output to indicate that the processor
has relinquished control of the local bus. When HLDA is
asserted, the processor will (or has) floated its data bus
and control signals allowing another bus master to drive the
signals directly.
NCS
(N.C.)
O
D
H(1)
R(1)
P(1)
Numerics Coprocessor Select
output is generated when
accessing a numerics coprocessor. NCS is not provided on
the QFP or SQFP packages. This signal does not exist on
the 80C188EB/80L188EB.
ERROR
(N.C.)
I
A(L)
D
ERROR
input that indicates the last numerics coprocessor
operation resulted in an exception condition. An interrupt
TYPE 16 is generated if ERROR is sampled active at the
beginning of a numerics operation. ERROR is not provided
on the QFP or SQFP packages. This signal does not exist
on the 80C188EB/80L188EB.
PEREQ
(N.C.)
I
A(L)
D
CoProcessor REQuest
signals that a data transfer
between an External Numerics Coprocessor and Memory is
pending. PEREQ is not provided on the QFP or SQFP
packages. This signal does not exist on the 80C188EB/
80L188EB.
UCS
O
D
H(1)
R(1)
P(1)
Upper Chip Select
will go active whenever the address of
a memory or I/O bus cycle is within the address limitations
programmed by the user. After reset, UCS is configured to
be active for memory accesses between 0FFC00H and
0FFFFFH.
LCS
O
D
H(1)
R(1)
P(1)
Lower Chip Select
will go active whenever the address of
a memory bus cycle is within the address limitations
programmed by the user. LCS is inactive after a reset.
P1.0/GCS0
P1.1/GCS1
P1.2/GCS2
P1.3/GCS3
P1.4/GCS4
P1.5/GCS5
P1.6/GCS6
P1.7/GCS7
O
D
H(X)/H(1)
R(1)
P(X)/P(1)
These pins provide a multiplexed function. If enabled, each
pin can provide a
Generic Chip Select
output which will go
active whenever the address of a memory or I/O bus cycle
is within the address limitations programmed by the user.
When not programmed as a Chip-Select, each pin may be
used as a general purpose output
Port.
As an output port
pin, the value of the pin can be read internally.
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
12
12
相關(guān)PDF資料
PDF描述
TN80C186EB20 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
TN80C186EB25 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
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TN80C188EB20 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
TN80C188EB25 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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