• 參數(shù)資料
    型號(hào)： TMX320F2810PGFA
    廠商： Texas Instruments, Inc.
    元件分類(lèi)： 數(shù)字信號(hào)處理
    英文描述： DIGITAL SIGNAL PROCESSORS
    中文描述： 數(shù)字信號(hào)處理器
    文件頁(yè)數(shù)： 55/103頁(yè)
    文件大?。?/td> 1341K
    代理商： TMX320F2810PGFA
    TMS320F2810, TMS320F2812
    DIGITAL SIGNAL PROCESSORS
    SPRS174B
    –
    APRIL 2001
    –
    REVISED SEPTEMBER 2001
    55
    POST OFFICE BOX 1443
    HOUSTON, TEXAS 77251
    –
    1443
    low-power modes block (continued)
    The low-power modes are controlled by the LPMCR0 register (see Table 41) and the LPMCR1 register (see
    Table 42).
    Table 41. LPMCR0 Register Bit Definitions
    BIT(S)
    NAME
    LPM
    TYPE
    RESET
    DESCRIPTION
    1,0
    R/W
    0,0
    These bits set the low power mode for the device.
    7:2
    QUALSTDBY
    R/W
    1:1
    Select number of OSCCLK clock cycles to qualify the selected inputs when
    waking the LPM from STANDBY mode:
    000000 = 2 OSCCLKs
    000001 = 3 OSCCLKs
    .
    111111 = 65 OSCCLKs
    15:8
    reserved
    R=0
    0:0
    These bits are cleared by a reset (XRS).
    The low power mode bits (LPM) are only valid when the IDLE instruction is executed. Therefore, the user must set the LPM bits to the appropriate
    mode before executing the IDLE instruction.
    Table 42. LPMCR1 Register Bit Definitions
    BIT(S)
    0
    NAME
    XINT1
    TYPE
    R/W
    RESET
    0
    DESCRIPTION
    1
    XNMI
    R/W
    0
    2
    WDINT
    R/W
    0
    3
    T1CTRIP
    R/W
    0
    4
    T2CTRIP
    R/W
    0
    5
    T3CTRIP
    R/W
    0
    6
    T4CTRIP
    R/W
    0
    7
    C1TRIP
    R/W
    0
    If the respective bit is set to 1, it will enable the selected signal to wake the
    If the res ective bit is set to 1, it will enable the selected signal to wake the
    device from STANDBY mode. If the bit is cleared, the signal will have no effect.
    8
    C2TRIP
    R/W
    0
    9
    C3TRIP
    R/W
    0
    10
    C4TRIP
    R/W
    0
    11
    C5TRIP
    R/W
    0
    12
    C6TRIP
    R/W
    0
    13
    SCIRXA
    R/W
    0
    14
    SCIRXB
    R/W
    0
    15
    CANRX
    R/W
    0
    These bits are cleared by a reset (XRS).
    P
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