參數(shù)資料
型號: TMX320F28044PZQ
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processor
中文描述: 數(shù)字信號處理器
文件頁數(shù): 83/107頁
文件大?。?/td> 784K
代理商: TMX320F28044PZQ
www.ti.com
6.9.2
GPIO - Input Timing
GPIO Signal
1
Sampling Window
Output From
Qualifier
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5
(C)
)
(A)
GPxQSELn = 1,0 (6 samples)
Sampling Period determined
by GPxCTRL[QUALPRD]
(B)
(D)
t
w(SP)
t
w(IQSW)
TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
A.
This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin
will be sampled).
The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.
B.
C.
D.
Figure 6-8. Sampling Mode
Table 6-11. General-Purpose Input Timing Requirements
MIN
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
QUALPRD = 0
QUALPRD
0
1t
c(SCO)
t
w(SP)
Sampling period
2t
c(SCO)
* QUALPRD
t
w(SP)
* (n
(1)
- 1)
t
w(IQSW)
Input qualifier sampling window
Synchronous mode
With input qualifier
2t
c(SCO)
t
w(GPI)(2)
Pulse duration, GPIO low/high
t
w(IQSW)
+ t
w(SP)
+ 1t
c(SCO)
(1)
(2)
"n" represents the number of qualification samples as defined by GPxQSELn register.
For t
w(GPI)
, pulse width is measured from V
IL
to V
IL
for an active low signal and V
IH
to V
IH
for an active high signal.
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Electrical Specifications
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