參數(shù)資料
型號(hào)： TMX320F28044GGMQ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processor
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 32/107頁(yè)
文件大小： 784K
代理商： TMX320F28044GGMQ
www.ti.com
INT12
MUX
INT11
INT2
INT1
CPU
(Enable)
(Flag)
INTx
INTx.8
PIEIERx(8:1)
PIEIFRx(8:1)
MUX
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
From
Peripherals or
External
Interrupts
(Enable)
(Flag)
IER(12:1)
IFR(12:1)
Global
Enable
INTM
1
0
PIEACKx
(Enable/Flag)
TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8
interrupts per group equals 96 possible interrupts. On the F28044 device, 43 of these are used by
peripherals as shown in
Table 3-8
.
Figure 3-4. Multiplexing of Interrupts Using the PIE Block
Table 3-8. PIE Peripheral Interrupts
(1)
PIE INTERRUPTS
CPU
INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
SEQ2INT
(ADC)
SEQ1INT
(ADC)
INT1
XINT2
XINT1
Reserved
EPWM8_TZINT
(ePWM8)
EPWM7_TZINT
(ePWM7)
EPWM6_TZINT
(ePWM6)
EPWM5_TZINT
(ePWM5)
EPWM4_TZINT
(ePWM4)
EPWM3_TZINT
(ePWM3)
EPWM2_TZINT
(ePWM2)
EPWM1_TZINT
(ePWM1)
INT2
EPWM8_INT
(ePWM8)
EPWM7_INT
(ePWM7)
EPWM6T_INTn
(ePWM6)
EPWM5_INT
(ePWM5)
EPWM4_INT
(ePWM4)
EPWM3_INT
(ePWM3)
EPWM2_INT
(ePWM2)
EPWM1_INT
(ePWM1)
INT3
INT4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
INT5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPITXINTA
(SPI-A)
SPIRXINTA
(SPI-A)
INT6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
INT7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I2CINT2A
(I2C-A)
I2CINT1A
(I2C-A)
INT8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
INT9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EPWM16_TZINT
(ePWM16)
EPWM15_TZINT
(ePWM15)
EPWM14_TZINT
(ePWM14)
EPWM13_TZINT
(ePWM13)
EPWM12_TZINT
(ePWM12)
EPWM11_TZINT
(ePWM11)
EPWM10_TZINT
(ePWM10)
EPWM9_TZINT
(ePWM9)
INT10
EPWM16_INT
(ePWM16)
EPWM15_INT
(ePWM15)
EPWM14_INT
(ePWM14)
EPWM13_INT
(ePWM13)
EPWM12_INT
(ePWM12)
EPWM11_INT
(ePWM11)
EPWM10_INT
(ePWM10)
EPWM9_INT
(ePWM9)
INT11
INT12
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(1)
Out of the 96 possible interrupts, 43 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1.
No peripheral within the group is asserting interrupts.
2.
No peripheral interrupts are assigned to the group (example PIE group 12).
Functional Overview
32
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