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參數(shù)資料
| 型號： | TMS66441410 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 4 194 304 4位/ 2 097 152 8位/ 1 048 576由16位4，銀行同步動態(tài)隨機(jī)存取記憶體 |
| 文件頁數(shù)： | 23/56頁 |
| 文件大小： | 958K |
| 代理商： | TMS66441410 |
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TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
23
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
ac timing requirements
(continued)
’664xx4-8
MIN
’664xx4-8A
MIN
’664xx4-10
MIN
UNIT
MAX
MAX
MAX
tAPR
Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR
command
tRP – (CL –1) * tCK
ns
tAPW
Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR
command
tRP + 1 tCK
ns
tT
tREF
Transition time
1
5
1
5
1
5
ns
Refresh interval
64
64
64
ms
nWR
Delay time, final data in of WRT operation to DEAC or DCAB
command
1
1
1
cycle
nCCD
nCDD
nCLE
Delay time, READ or WRT command to an interrupting command
1
1
1
cycle
Delay time, CS low or high to input enabled or inhibited
0
0
0
0
0
0
cycle
Delay time, CKE high or low to CLK enabled or disabled
1
1
1
1
1
1
cycle
nCWL
Delay time, final data in of WRT command to READ, READ-P, WRT, or
WRT-P command
1
1
1
cycle
nDID
nDOD
Delay time, ENBL or MASK command to enabled or masked data in
0
0
0
0
0
0
cycle
Delay time, ENBL or MASK command to enabled or masked data out
2
2
2
2
2
2
cycle
nHZP2
Delay time, DEAC or DCAB command to DQ in
high-impedance state
CAS latency = 2
2
2
2
cycle
nHZP3
Delay time, DEAC or DCAB command to DQ in
high-impedance state
CAS latency = 3
3
3
3
cycle
nWCD
See Parameter Measurement Information for load circuits (see Figure 9).
All references are made to the rising transition of CLK, unless otherwise noted.
Delay time, WRT command to first data in
0
0
0
0
0
0
cycle
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| TMS6644148 | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS6644148A | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS6644148 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS6644148A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS664414DGE-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X4MX4|CMOS|TSOP|54PIN|PLASTIC |
| TMS664414DGE-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X4MX4|CMOS|TSOP|54PIN|PLASTIC |
| TMS664414DGE-8A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X4MX4|CMOS|TSOP|54PIN|PLASTIC |
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