參數(shù)資料
型號(hào): TMS32C6411AGLZ
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: FIXED POINT DIGITAL SIGNAL PROCESSOR
中文描述: 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù): 79/119頁
文件大?。?/td> 1742K
代理商: TMS32C6411AGLZ
SPRS196H MARCH 2002 REVISED JULY 2004
79
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
ECLKOUTx
CEx
BE[3:0]
EA[22:3]
ED[31:0]
ARE/SDCAS/SADS/SRE§
AOE/SDRAS/SOE§
AWE/SDWE/SWE§
BE1
BE2
BE3
BE4
Q1
Q2
Q3
Q4
9
1
4
5
8
9
6
7
3
1
2
EA1
EA2
EA4
8
READ latency = 2
EA3
The read latency and the length of CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIF CE Space
Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0.
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).
Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
§ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during
programmable synchronous interface accesses.
Figure 24. Programmable Synchronous Interface Read Timing (With Read Latency = 2)
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