參數(shù)資料
型號: TMS320VC549PGE
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSOR
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 96/123頁
文件大?。?/td> 1205K
代理商: TMS320VC549PGE
www.ti.com
WAKE INT
(A)
XCLKOUT
Addres/Data
(internal)
t
d(WAKEIDLE)
t
w(WAKEINT)
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
6.8.4
Low-Power Mode Wakeup Timing
Table 6-14
shows the timing requirements,
Table 6-15
shows the switching characteristics, and
Figure 6-11
shows the timing diagram for IDLE mode.
Table 6-14. IDLE Mode Timing Requirements
(1)
MIN
NOM
MAX
UNIT
Without input qualifier
With input qualifier
2t
c(SCO)
5t
c(SCO)
+ t
w(IQSW)
t
w(WAKE-INT)
Pulse duration, external wake-up signal
cycles
(1)
For an explanation of the input qualifier parameters, see
Table 6-13
.
Table 6-15. IDLE Mode Switching Characteristics
(1)
PARAMETER
Delay time, external wake signal to pro-
gram execution resume
(2)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
20t
c(SCO)
cycles
Wake-up from Flash
Flash module in active state
20t
c(SCO)
+ t
w(IQSW)
1050t
c(SCO)
1050t
c(SCO)
+ t
w(IQSW)
t
d(WAKE-IDLE)
cycles
Wake-up from Flash
Flash module in sleep state
20t
c(SCO)
cycles
Wake-up from SARAM
20t
c(SCO)
+ t
w(IQSW)
(1)
(2)
For an explanation of the input qualifier parameters, see
Table 6-13
.
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
A.
WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6-11. IDLE Entry and Exit Timing
Table 6-16. STANDBY Mode Timing Requirements
TEST CONDITIONS
Without input qualification
With input qualification
(1)
MIN
NOM
MAX
UNIT
3t
c(OSCCLK)
t
w(WAKE-
INT)
Pulse duration, external
wake-up signal
cycles
(2 + QUALSTDBY) * t
c(OSCCLK)
(1)
QUALSTDBY is a 6-bit field in the LPMCR0 register.
Electrical Specifications
96
相關PDF資料
PDF描述
TMS320LF2407PG DSP CONTROLLERS
TMS320LF2407PGE 1A, 52kHz (250khz Max) Current Mode PWM Control Circuit with 8.4V UVLO Threshold and 96% Max Duty Cycle<sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup> ; Package: 8 LEAD PDIP; No of Pins: 8; Container: Rail; Qty per Container: 50
TMS320LC2404 1A, 52kHz (250khz Max) Current Mode PWM Control Circuit with 16V UVLO Threshold and 96% Max Duty Cycle<sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup> ; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Rail; Qty per Container: 98
TMS320LC2406PG DSP CONTROLLERS
TMS320LC2406PGE 1A, 52kHz (250khz Max) Current Mode PWM Control Circuit with 16V UVLO Threshold and 96% Max Duty Cycle<sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup> ; Package: 8 LEAD PDIP; No of Pins: 8; Container: Rail; Qty per Container: 50
相關代理商/技術參數(shù)
參數(shù)描述
TMS320VC549PGE-100 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Dig Sig Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
TMS320VC549PGE-100 制造商:Texas Instruments 功能描述:DSP PROCESSOR 320VC549 TQFP144
TMS320VC549PGE-100G4 制造商:Rochester Electronics LLC 功能描述:- Bulk
TMS320VC549PGE100W 制造商:Rochester Electronics LLC 功能描述:- Bulk
TMS320VC549PGE-120 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
  • <thead id="v7980"></thead>
  • <label id="v7980"></label>
  • <thead id="v7980"><dfn id="v7980"><tbody id="v7980"></tbody></dfn></thead>