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TMS320F28044
Digital Signal Processor
SPRS357A–AUGUST 2006–REVISED OCTOBER 2006
List of Figures
2-1
100-Pin PZ LQFP (Top View)
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11
100-Ball GGM and ZGM MicroStar BGA (Bottom View)
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12
Functional Block Diagram
........................................................................................................
19
F28044 Memory Map
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20
External and PIE Interrupt Sources
.............................................................................................
30
Multiplexing of Interrupts Using the PIE Block
................................................................................
31
Clock and Reset Domains
.......................................................................................................
33
OSC and PLL Block Diagram
...................................................................................................
35
Using a 3.3-V External Oscillator
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35
Using a 1.8-V External Oscillator
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35
Using the Internal Oscillator
.....................................................................................................
35
Watchdog Module
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38
CPU-Timers
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40
CPU-Timer Interrupt Signals and Output Signal
..............................................................................
41
Multiple PWM Modules
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42
ePWM Sub-Modules Showing Critical Internal Signal Interconnections
...................................................
47
Block Diagram of the ADC Module
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49
ADC Pin Connections With Internal Reference
...............................................................................
50
ADC Pin Connections With External Reference
..............................................................................
51
Serial Communications Interface (SCI) Module Block Diagram
............................................................
55
SPI Module Block Diagram (Slave Mode)
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58
I
2
C Peripheral Module Interfaces
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60
GPIO MUX Block Diagram
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61
Qualification Using Sampling Window
..........................................................................................
64
Example of TMS320x280x Device Nomenclature
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66
Emulator Connection Without Signal Buffering for the DSP
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73
3.3-V Test Load Circuit
...........................................................................................................
75
Clock Timing
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77
Power-on Reset
...................................................................................................................
78
Warm Reset
........................................................................................................................
79
Example of Effect of Writing Into PLLCR Register
...........................................................................
80
General-Purpose Output Timing
................................................................................................
80
Sampling Mode
....................................................................................................................
81
General-Purpose Input Timing
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82
IDLE Entry and Exit Timing
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83
STANDBY Entry and Exit Timing Diagram
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84
HALT Wake-Up Using GPIOn
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85
PWM Hi-Z Characteristics
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86
ADCSOCAO or ADCSOCBO Timing
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87
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
List of Figures
4
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