參數(shù)資料
型號: TMS320DM648ZUT9
廠商: Texas Instruments
文件頁數(shù): 73/190頁
文件大小: 0K
描述: IC DGTL MEDIA PROC 529-FCBGA
標(biāo)準(zhǔn)包裝: 84
系列: TMS320DM64x, DaVinci™
類型: 定點
接口: 主機接口,I²C,McASP,PCI,SPI,UART
時鐘速率: 900MHz
非易失內(nèi)存: ROM(64 kB)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 1.8V,3.3V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 529-BFBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 529-FCBGA(19x19)
包裝: 托盤
產(chǎn)品目錄頁面: 715 (CN2011-ZH PDF)
配用: 296-23122-ND - PLATFORM DEV DGTL VIDEO DM648
其它名稱: 296-26858-5
TMS320DM648ZUT9-ND
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SPRS372H – MAY 2007 – REVISED APRIL 2012
The Ethernet Subsystem conforms to the IEEE 802.3-2002 standard. Deviating from this standard, the
GMAC module does not use the transmit coding error signal MTXER. Instead of driving the error pin when
an underflow condition occurs on a transmitted frame, the GMAC generates an incorrect checksum by
inverting the frame CRC, so that the transmitted frame will be detected as an error by the network.
In networking systems, packet transmission and reception are critical tasks. The communications port
programming interface (CPPI) protocol maximizes the efficiency of interaction between the host software
and communications modules. The CPPI block contains 2048 words of 32-bit buffer descriptor memory
that holds up to 512 buffer descriptors.
After reset, initialization, configuration, and auto-negotiation, the host C64x+ DSP may initiate Ethernet
transmit and receive operations.
Transmit operations are initiated by C64x+ DSP writes to the appropriate transmit channel head
descriptor pointer contained in the CPDMA block. The CPDMA TX controller then fetches the first
packet in the packet chain from memory in accordance with the CPPI protocol for the GMAC to
process before sending to the SGMII.
Receive operations are initiated by C64x+ DSP writes to the appropriate receive channel head
descriptor pointer. The CPDMA RX controller then writes packets to memory in accordance with the
CPPI protocol.
DSP writes may be write-protected to the Ethernet Subsystem configuration registers from addresses
0x02D0 0000 - 0x02D0 4FFF (3PGSW, MDIO, SGMII0, SGMII1, control), and the CPPI RAM. The
Ethernet Subsystem setting in the PSC is also write-protected. A specific 32-bit lock code (0x4C6F436B)
and a 32-bit unlock code (0x6F50654E) written to ESS_LOCK register will activate or clear this option,
respectively. See Section 3.2.5 and Section 3.2.7
The 3-port gigabit switch block contains the following functions:
3-port gigabit switch: performs packet forwarding and routing functions, one port is internally connected
to the C64x+ DSP and two ports are brought out externally
CPDMA: performs high-speed DMA transfers with RX and TX CPPI buffers in local memory, including
channel setup and channel teardown
GMAC (Gigabit Ethernet MAC):
Uses Rx packet FIFO, and a TX packet FIFO to improve data transfer efficiency
Handles processing of Ethernet packet data, frames, and headers
Includes flow control
Provides statistics collection and reporting
The address lookup engine (ALE) processes all received packets to determine where (that is, which
packet location) to forward the packet. The ALE uses the incoming packet received port number,
destination address, source address, length/type, and VLAN information to determine how the packet
should be forwarded. The ALE outputs the port mask to the switch fabric that indicates to which port(s)
the packet should be forwarded.
6.19.2 Interrupt Controller and Pacing Interrupts
The interrupt control block selects the interrupts from the 3-port gigabit switch and MDIO modules for
output to the C64x+ DSP. The miscellaneous interrupt is an immediate (non-paced) interrupt selected
from the miscellaneous interrupts (host error level, statistics level, MDIO User [2], MDIO link [2]).
The eight RX interrupts and eight TX interrupts can be paced. The 8 RX threshold interrupts and the
miscellaneous interrupts are not paced. The interrupt pacing feature limits the number of interrupts that
occur during a given period of time. For heavily loaded systems in which interrupts can occur at a very
high rate, the performance benefit is significant due to minimizing the overhead associated with servicing
each interrupt. Interrupt pacing increases the C64x+ DSP cache hit ratio by minimizing the number of
times that large interrupt service routines are moved to and from the DSP instruction cache.
MDIO
164
Peripheral Information and Electrical Specifications
Copyright 2007–2012, Texas Instruments Incorporated
Product Folder Link(s): TMS320DM647 TMS320DM648
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TMS320DM648ZUTA6 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Digital Media Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320DM648ZUTA8 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Digital Media Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320DM648ZUTD1 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Digital Media Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320DM648ZUTD7 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Digital Media Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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