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TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
88
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2
Strobe = 3
Not Ready
Hold = 2
BE
Address
Write Data
10
8
7
6
9
ECLKOUTx
CEx
AEA[22:3] or BEA[20:1]
AED[63:0] or BED[15:0]
ABE[7:0] or BBE[1:0]
ARDY
AOE/SDRAS/SOE
ARE/SDCAS/SADS/SRE
AWE/SDWE/SWE
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous
memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and
BAWE (for EMIFB)].
AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 23. Asynchronous Memory Write Timing for EMIFA and EMIFB