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WAKE INT
(A)
XCLKOUT
Address/Data
(internal)
t
d(WAKEIDLE)
t
w(WAKEINT)
TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
6.9.4
Low-Power Mode Wakeup Timing
Table 6-12
shows the timing requirements,
Table 6-13
shows the switching characteristics, and
Figure 6-10
shows the timing diagram for IDLE mode.
Table 6-12. IDLE Mode Timing Requirements
(1)
MIN
NOM
MAX
UNIT
Without input qualifier
With input qualifier
2t
c(SCO)
5t
c(SCO)
+ t
w(IQSW)
t
w(WAKE-INT)
Pulse duration, external wake-up signal
cycles
(1)
For an explanation of the input qualifier parameters, see
Table 6-11
.
Table 6-13. IDLE Mode Switching Characteristics
(1)
PARAMETER
Delay time, external wake signal to
program execution resume
(2)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
20t
c(SCO)
cycles
Wake-up from Flash
–
Flash module in active state
20t
c(SCO)
+ t
w(IQSW)
1050t
c(SCO)
1050t
c(SCO)
+ t
w(IQSW)
t
d(WAKE-IDLE)
cycles
Wake-up from Flash
–
Flash module in sleep state
20t
c(SCO)
cycles
Wake-up from SARAM
20t
c(SCO)
+ t
w(IQSW)
(1)
(2)
For an explanation of the input qualifier parameters, see
Table 6-11
.
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
A.
WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6-10. IDLE Entry and Exit Timing
Table 6-14. STANDBY Mode Timing Requirements
TEST CONDITIONS
Without input qualification
With input qualification
(1)
MIN
NOM
MAX
UNIT
3t
c(OSCCLK)
Pulse duration, external
wake-up signal
t
w(WAKE-INT)
cycles
(2 + QUALSTDBY) * t
c(OSCCLK)
(1)
QUALSTDBY is a 6-bit field in the LPMCR0 register.
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Electrical Specifications
85