參數(shù)資料
型號(hào): TMP320F28044ZGMA
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processor
中文描述: 數(shù)字信號(hào)處理器
文件頁數(shù): 24/107頁
文件大?。?/td> 784K
代理商: TMP320F28044ZGMA
www.ti.com
3.2.3
Peripheral Bus
3.2.4
Real-Time JTAG and Analysis
3.2.5
Flash
3.2.6
M0, M1 SARAMs
3.2.7
L0, L1 SARAMs
TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the
F28044 device adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge
multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16
address lines and 16 or 32 data lines and associated control signals. Two versions of the peripheral bus
are supported on the F28044. One version only supports 16-bit accesses (called peripheral frame 2). The
other version supports both 16- and 32-bit accesses (called peripheral frame 1).
The F28044 device implements the standard IEEE 1149.1 JTAG interface. Additionally, the device
supports real-time mode of operation whereby the contents of memory, peripheral and register locations
can be modified while the processor is running and executing code and servicing interrupts. The user can
also single step through non-time critical code while enabling time-critical interrupts to be serviced without
interference. The F28044 implements the real-time mode in hardware within the CPU. This is a unique
feature to the F28044, no software monitor is required. Additionally, special analysis hardware is provided
which allows the user to set hardware breakpoint or data/address watch-points and generate various
user-selectable break events when a match occurs.
The F28044 contains 64K x 16 of embedded flash memory, segregated into four 16K X 16 sectors. Both
devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 – 0x3D 7BFF. The
user can individually erase, program, and validate a flash sector while leaving other sectors untouched.
However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that
erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve
higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used
to execute code or store data information. Note that addresses 0x3F7FF0 – 0x3F7FF5 are reserved for
data variables and should not contain program code.
NOTE
The F28044 Flash and OTP wait-states can be configured by the application. This allows
applications running at slower frequencies to configure the flash to use fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait-state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers,
see the
TMS320x280x, 2801x, 2804x System Control and Interrupts Reference Guide
(literature number SPRU712).
The F28044 device contains these two blocks (M0/M1) of single access memory, each 1K x 16 in size.
The stack pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other
memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can use
M0 and M1 to execute code or for data variables. The partitioning is performed within the linker. The C28x
device presents a unified memory map to the programmer. This makes for easier programming in
high-level languages.
The F28044 device contains an additional 8K x 16 of single-access RAM, divided into 2 blocks (L0-4K,
L1-4K). Each block can be independently accessed to minimize CPU pipeline stalls. Each block is
mapped to both program and data space.
Functional Overview
24
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