參數(shù)資料
型號(hào): TMP320F28044GGMS
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processor
中文描述: 數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 29/107頁(yè)
文件大?。?/td> 784K
代理商: TMP320F28044GGMS
www.ti.com
3.2.20
Serial Port Peripherals
3.3
Register Map
TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
The F28044 device supports the following serial communication peripherals:
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multi-device communications are supported by the master/slave
operation of the SPI. On the F28044 device, the SPI contains a 16-level receive and
transmit FIFO for reducing interrupt servicing overhead.
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the F28044 device, the SCI contains a 16-level receive and transmit
FIFO for reducing interrupt servicing overhead.
The inter-integrated circuit (I
2
C) module provides an interface between a DSP and other
devices compliant with Philips Semiconductors Inter-IC bus (I
2
C-bus) specification version
2.1 and connected by way of an I
2
C-bus. External components attached to this 2-wire
serial bus can transmit/receive up to 8-bit data to/from the DSP through the I
2
C module.
On the F28044 device, the I
2
C contains a 16-level receive and transmit FIFO for reducing
interrupt servicing overhead.
SCI:
I
2
C:
The F28044 device contains three peripheral register spaces. The spaces are categorized as follows:
Peripheral
Frame 0:
Peripheral
Frame 1
Peripheral
Frame 2:
These are peripherals that are mapped directly to the CPU memory bus.
See
Table 3-4
These are peripherals that are mapped to the 32-bit peripheral bus.
See
Table 3-5
These are peripherals that are mapped to the 16-bit peripheral bus.
See
Table 3-6
Table 3-4. Peripheral Frame 0 Registers
(1)(2)
NAME
ADDRESS RANGE
0x0880 - 0x09FF
SIZE (x16)
384
ACCESS TYPE
(3)
Device Emulation Registers
EALLOW protected
EALLOW protected
CSM Protected
EALLOW protected
FLASH Registers
(4)
0x0A80 - 0x0ADF
96
Code Security Module Registers
ADC Result Registers (dual-mapped)
CPU-TIMER0/1/2 Registers
PIE Registers
PIE Vector Table
0x0AE0 - 0x0AEF
0xB00 - 0xB0F
0x0C00 - 0x0C3F
0x0CE0 - 0x0CFF
0x0D00 - 0x0DFF
16
16
64
32
256
Not EALLOW protected
EALLOW protected
(1)
(2)
(3)
Registers in Frame 0 support 16-bit and 32-bit accesses.
Missing segments of memory space are reserved and should not be used in applications.
If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
The Flash Registers are also protected by the Code Security Module (CSM).
(4)
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