參數(shù)資料
型號(hào)： TMP320C6205ZHKA200
廠商： Texas Instruments, Inc.
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 36/72頁(yè)
文件大?。?/td> 1143K
代理商： TMP320C6205ZHKA200
SPRS106G OCTOBER 1999 REVISED JULY 2006
36
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN
§
(see Figure 12)
200
NO.
PLL mode x4,
x6, x7, x8, x9,
x10, x11
PLL mode
x1
UNIT
MIN
MAX
MIN
MAX
1
tc(CLKIN)
tw(CLKINH)
tw(CLKINL)
tt(CLKIN)
Cycle time, CLKIN
5 * M
5
ns
2
Pulse duration, CLKIN high
0.4C
0.45C
ns
3
Pulse duration, CLKIN low
0.4C
0.45C
ns
4
Transition time, CLKIN
5
0.6
ns
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
M = the PLL multiplier factor (x4, x6, x7, x8, x9, x10, or x11). For more details, see the clock PLL section of this data sheet.
§C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
CLKIN
1
2
3
4
4
Figure 12. CLKIN Timings
timing requirements for PCLKIN
(see Figure 13)
NO.
200
UNIT
MIN
MAX
1
tc(PCLK)
tw(PCLKH)
tw(PCLKL)
tsr(PCLK)
Cycle time, PCLK
30
ns
2
Pulse duration, PCLK high
11
ns
3
Pulse duration, PCLK low
v/
t slew rate, PCLK
11
ns
4
1
4
V/ns
When the 5-V PCI clamp is used, the reference points for the rise and fall transitions are measured VILP MAX and VIHP MIN for 5 V operation.
When the 3.3-V PCI clamp is used, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN for 3.3 V
operation.
PCLK
1
2
3
4
4
2 V MIN
Peak to Peak for
5V signaling
or
0.4 VIOP MIN
Peak to Peak for
3V signaling
Figure 13. PCLK Timings
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