參數(shù)資料
型號： TMDS461PZT
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： PLASTIC, TQFP-100
文件頁數(shù)： 25/43頁
文件大?。?/td> 3111K
代理商： TMDS461PZT
A DTV Supporting an Active CEC Link
SINK
HDMIRX
DDC_SDA
DDC_SCL
5 V
47kW
3.3 V
4.7kW
CEC
4.02 k W 10%
E-EDID
mController
HPD1
SDA1
SCL1
HPD2
SDA2
SCL2
HPD3
SDA3
SCL3
Local_SCL
Local_SDA
5V_Ind
SDA_SINK
SCL_SINK
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
VSADJ
GND
CEC
PHY
1 kW
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
SOURCE1
SOURCE2
SOURCE3
A11/B11
A12/B12
A13/B13
A14/B14
A21/B21
A22/B22
A23/B23
A24/B24
A31/B31
A32/B32
A33/B33
A34/B34
VCC
(3.3V)
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
5V_PWR[1]
5V_PWR[2]
5V_PWR[3]
5 V
47kW
CEC E-EDID
HPD4
SDA4
SCL4
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
SOURCE4
A41/B41
A42/B42
A43/B43
A44/B44
5V_PWR[4]
HPD_SINK
CEC
LOGIC
I
2C INTERFACE NOTES
www.ti.com ............................................................................................................................................................................................... SLLS915 – JANUARY 2009
In Figure 37, the CEC PHY and CEC LOGIC functions are included. The DTV can initiate and/or react to CEC
signals from its remote control or other audio/video products on the same CEC bus. All sources must have their
own CEC physical address to support the full functionality of the CEC link.
A source reads its CEC physical address stored its E-EDID memory after receiving a logic-high from the HPD
feedback. When HPD is high, the sink-assigned CEC physical address should be maintained. Otherwise, when
HPD is low, the source sets CEC physical address value to (F.F.F.F).
Figure 37. Four-Port HDMI-Enabled DTV With TMDS461 – CEC Commands Active
The I2C interface is used to access the internal registers of the TMDS461. I2C is a two-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines
are pulled high. All the I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA and
SCL. A master device, usually a micro controller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addressing information. The master also generates specific
conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on
the bus under control of the master device. The TMDS461 works as a slave and supports standard-mode
transfer (100 kbps).
Copyright 2009, Texas Instruments Incorporated
31
Product Folder Link(s) :TMDS461
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