參數(shù)資料
型號(hào)： TMDS261BPAGR
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 37/49頁(yè)
文件大小： 11321K
代理商： TMDS261BPAGR
SLLS987 – SEPTEMBER 2009 .......................................................................................................................................................................................... www.ti.com
Table 9. I2C Register 0x02 Lookup Table (continued)
BIT
VALUE
STATE
DEFAULT
DESCRIPTION
5:4
Bit 4
Bit 3
OVS Control Status Indicator
0
Indicates DDC sink side VOL and VIL offset range 2: VIL2 (max): 0.4 V, VOL2 (max): 0.6 V
0
1
X
Indicates DDC sink side VOL and VIL offset range 3: VIL3 (max): 0.3 V, VOL3 (max): 0.5 V
1
Indicates DDC sink side VOL and VIL offset range 1: VIL1 (max): 0.4 V, VOL1 (max): 0.7 V
3:2
Bit 3
Bit 2
Output Edge Rate Status Control
1
Indicates fastest TMDS output rise and fall time setting + 120 ps approximately (slowest rise
and fall time setting)
1
0
Indicates fastest TMDS output rise and fall time setting + 100 ps approximately
0
1
Indicates fastest TMDS output rise and fall time setting + 50 ps approximately
0
X
Indicates fastest TMDS output rise and fall time setting
1:0
Bit 1
Bit 0
Power-Mode Status Indicator
1
0
Indicates device enters low-power mode
1
Indicates device enters low-power mode
0
1
Reserved
0
X
Indicates device is in normal-power mode
Register 0x02 is read-only.
Table 10. I2C Register 0x03 Lookup Table
BIT
VALUE
STATE
DEFAULT
DESCRIPTION
7
1
Clock
Clock-detect circuit disabled. For HDMI compliance testing (TMDS termination-voltage test),
detect
clock-detect feature should be disabled. In this mode, the terminations on the TMDS input data
disabled
lines are always connected when the port is selected.
0
Clock
X
Clock-detect circuit enabled. It is recommended that the TMDS261B is used in this default
detect
mode during normal operation where clock detect circuit is enabled. The terminations on the
enabled
TMDS input data lines are connected only when a valid TMDS clock is detected on the selected
port.
6:5
X
RSVD
Reserved
4
0
RSVD
X
Note: Do not write a 1 to this bit.
3:0
0
RSVD
X
Reserved
Register 0x03 is read/write. For disabling clock detect, the value of 80h or 1000 0000b can be written to register
0x03.
Table 11. I2C Register 0x04 Lookup Table
BIT
VALUE
STATE
DEFAULT
DESCRIPTION
7
1
Clock
A valid clock signal is detected on the selected port. If clock detect is disabled in register
detected
0x03, then bit 7 of register 0x04 is always 1.
0
No clock
X
The selected port does not have a valid clock signal.
detect
6:5
X
RSVD
Reserved
4
0
RSVD
X
This bit should always read 0
3:0
0
RSVD
X
Reserved
Register 0x04 is read-only.
Table 12. I2C Register 0x05 Lookup Table
BIT
VALUE
STATE
DEFAULT
DESCRIPTION
7:0
—
RSVD
X
Reserved. Read-only, value is indeterministic.
42
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s) :TMDS261B
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