參數(shù)資料
型號： TMDS261BPAG
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁數(shù)： 32/49頁
文件大?。?/td> 11321K
代理商： TMDS261BPAG
SCL
SDA
MSB
Slave Address
Acknowledge
Data
Acknowledge
Stop
123456789123456789
T0396-01
S
Slave Address
W
A
Data
A
Data
A
P
FromReceiver
From Transmitter
A =No Acknowledge(SDA High)
A = Acknowledge
S=StartCondition
P =StopCondition
W=Write
R0007-01
Acknowledge
(FromReceiver)
Start
Condition
Acknowledge
(Receiver)
Acknowledge
(Receiver)
SDA
Stop
Condition
I CDevice Addressand
Read/WriteBit
2
FirstDataByte
Other
DataBytes
LastDataByte
A6
ACK
A5
A1
A0
R/W
D7
D6
D1
D0 ACK
D7
D6
D1
D0
ACK
T0397-01
S
Slave Address
R
A
Data
A
Data
A
P
Receiver
Transmitter
A =No Acknowledge(SDA High)
A = Acknowledge
S=StartCondition
P =StopCondition
W=Write
R=Read
R0008-01
SLLS987 – SEPTEMBER 2009 .......................................................................................................................................................................................... www.ti.com
Figure 53. I2C Address, Data Cycle(s), and Stop
During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle so
that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the
receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting
device after the last byte is transferred. An example of a write cycle can be found in Figure 54 and Figure 55.
Note that the TMDS261B allows multiple write transfers to occur. See the Example – Writing to the TMDS261
section for more information.
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not-acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 56 and Figure 57.
See the Example – Reading from the TMDS261 section for more information.
Figure 54. I2C Write Cycle
Figure 55. Multiple-Byte Write Transfer
Figure 56. I2C Read Cycle
38
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s) :TMDS261B
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