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參數(shù)資料
| 型號： | TMC2242B |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 12-bit In/16-bit Out, 60 MHz Digital Half-Band Interpolating/Decimating Filter(12位輸入/16位輸出,60 MHz 數(shù)字式半波段插補(bǔ)/分樣濾波器) |
| 中文描述： | 12位In/16-bit輸出，60兆赫數(shù)字半帶插值/抽取濾波器（12位輸入/ 16位輸出，60兆赫數(shù)字式半波段插補(bǔ)/分樣濾波器） |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 86K |
| 代理商： | TMC2242B |
PRODUCT SPECIFICATION
TMC2242A/TMC2242B
2
The filter response is flat to within
0.22 x f
s
, with stopband attenuation greater than 59.4 dB
from 0.28 x f
s
to the Nyquist frequency. The response is 6 dB
down at 0.25 x f
s
. Symmetric-coefficient filters such as the
TMC2242A and TMC2242B have linear phase response.
Full compliance with the CCIR-601 standard of 12 dB atten-
uation at 0.25 x f
s
is achieved by cascading two parts.
±
0.01 dB from 0.00 to
The TMC2242A and TMC2242B are fabricated on an
advanced submicron CMOS process. They are available in a
44-lead J-lead PLCC package. Performance is guaranteed
from 0
°
C to 70
°
C.
Functional Description
The TMC2242A and TMC2242B implement a fixed-coeffi-
cient linear-phase Finite Impulse Response (FIR) filter of 55
effective taps, with special rate-matching input and output
structures to facilitate 2:1 decimation and 1:2 interpolation.
The faster of either the input or output registers will operate
at the guaranteed maximum clock rate (speed grade). The
total internal pipeline latency from the input of an impulse to
the corresponding output peak (digital group delay) is 34
cycles; the 55-value output response begins after 7 clock
cycles and ends after 61 cycles.
To perform interpolation, the chip slows the effective input
register clock rate to half the output rate. It internally inserts
zeroes between the incoming data samples to "pad" the input
data rate to match the output rate.
To perform decimation, the chip sets the output register
clock rate to half of the input rate. One output is then
obtained for every two inputs.
For interpolation, the user should bring SYNC HIGH for at
least one clock cycle, returning it LOW with the first desired
input data value. When interpolating, the chip will then con-
tinue to accept a new data input on each alternate rising edge
of the clock. When decimating, the chip will present one out-
put value for every two clock cycles. The user may leave
SYNC LOW or toggle it once per rising clock edge, with
equivalent performance.
The output data format is two's complement if TCO is
HIGH, inverted offset binary if LOW. The user can tailor the
output data word width to his/her system requirements using
the Rounding control. As shown in Table 4, the output is
half-LSB rounded to the resolution selected by the value of
RND
2-0
. The asynchronous three-state output enable control
simplifies connection to a data bus with other drivers.
Table 1. Operating Modes
Note:
1. With 15-bit overflow protection. All other modes on both
parts limit to 16 bits.
DEC
0
0
1
1
INT
0
1
0
1
TMC2242A
Equal Rate
Decimate
Interpolate (-6 dB)
Equal Rate
TMC2242B
Interpolate (0 dB)
Decimate
Interpolate (-6 dB)
Equal Rate
1
Pin Assignments
65-2242A-02
SO
12
SO
11
SO
10
SO
9
SO
8
GND
V
DD
SO
7
SO
6
SO
5
SO
4
GND
V
DD
SI
10
SI
9
SI
8
SI
7
SI
6
SI
5
SI
4
SI
3
V
DD
S
1
S
1
S
1
O
T
D
I
S
C
G
S
1
S
3
S
2
S
1
S
0
R
2
R
1
R
0
S
0
S
1
S
2
G
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
1
1
2
2
2
2
2
2
2
2
2
6
5
4
3
2
1
4
4
4
4
4
TMC2242A
TMC2242B
65-2242A-02
SO
12
SO
11
SO
10
SO
9
SO
8
GND
V
DD
SO
7
SO
6
SO
5
SO
4
GND
V
DD
SI
10
SI
9
SI
8
SI
7
SI
6
SI
5
SI
4
SI
3
V
DD
S
1
S
1
S
1
O
T
D
I
S
C
G
S
1
S
3
S
2
S
1
S
0
R
2
R
1
R
0
S
0
S
1
S
2
G
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
1
1
1
1
1
1
1
1
2
2
2
4
4
4
4
4
3
3
3
3
3
3
TMC2242A
TMC2242B
Description
(continued)
44 Lead PLCC
44 Lead MQFP
相關(guān)PDF資料 |
PDF描述 |
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| TMC2242CKTC | Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz |
| TMC2242CKTC1 | Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz |
| TMC2242C | Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz |
| TMC2242CR2C | Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz |
| TMC2242CR2C1 | TRANS PNP 20V 5A SOT-89 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2242BKTC | 功能描述:視頻 IC Interp/Decim Filter Digital HB 12B/16B RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TMC2242BKTC1 | 功能描述:視頻 IC Interp/Decim Filter Digital HB 12B/16B RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TMC2242BKTC2 | 功能描述:視頻 IC Interp/Decim Filter Digital HB 12B/16B RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TMC2242BR2C | 功能描述:視頻 IC Interp/Decim Filter Digital HB 12B/16B RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TMC2242BR2C1 | 功能描述:視頻 IC Interp/Decim Filter Digital HB 12B/16B RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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