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參數(shù)資料
| 型號： | TMC22091 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Digital Video Encoders(數(shù)字視頻編碼器) |
| 中文描述： | 數(shù)字視頻編碼器（數(shù)字視頻編碼器） |
| 文件頁數(shù)： | 15/60頁 |
| 文件大小： | 293K |
| 代理商： | TMC22091 |
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PRODUCT SPECIFICATION
TMC22091/TMC22191
15
Control Register Definitions
(continued)
Interface Control Register (02)
7
6
5
4
3
2
1
0
VITSEN
SHCY
TBASE
SOUT
FBDIS
PDCDIR
FLDLK
Reg
02
Bit
7
Name
VITSEN
Function
VITS lines enable. When LOW, all UBB lines in the vertical interval are black
burst regardless of input data. When HIGH, all UBB lines in the vertical interval
become UVV active video and are dependent upon input data.
Short-cycle test mode. When LOW, normal operation is enabled. when HIGH,
EH (equalization pulse HIGH length) and SL (vertical sync LOW length) are
shortened by 256.
Time-base source select. These two bits set up the TMC22x91 for either
genlock or frame buffer control of timing. When bits 5 and 4 are:
02
6
SHCY
02
5-4
TBASE
0 0 the encoder counts out its own time-base from input clock PXCK.
0 1 the encoder locks to synchronizing signals from external genlock.
1 0 the encoder locks to synchronizing signals from frame buffer controller.
Sync output mode select. When LOW, VHSYNC and VVSYNC output separate
horizontal and vertical sync pulses. When HIGH, composite sync (H and V) is
output on VVSYNC while horizontal sync is output on VHSYNC.
Frame buffer signals enable. When LOW, VVSYNC and VHSYNC outputs to
frame buffer are enabled. When HIGH, VVSYNC and VHSYNC outputs to
frame buffer are disabled.
PDC master/slave select. When LOW, PDC is an output where the encoder is
requesting data from the frame buffer. When HIGH, PDC is an input, and
directs the encoder to accept data from the frame buffer.
Field lock select. When LOW, (in Slave mode) the encoder locks to each new
field. When HIGH, the encoder locks to field 1 only.
02
3
SOUT
02
2
FBDIS
02
1
PDCDIR
02
0
FLDLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMC22191 | Digital Video Encoders(數(shù)字視頻編碼器) |
| TMC2242A | Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz |
| TMC2242BKTC | Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz |
| TMC2242BKTC1 | Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz |
| TMC2242BKTC2 | Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC22091KHC | 功能描述:視頻 IC D/V Encoder Layering Engine RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TMC22091R0C | 功能描述:視頻 IC D/V Encoder Layering Engine RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TMC22091R0CT | 功能描述:視頻 IC D/V Encoder Layering Engine RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TMC22091ROC-T | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC22151AKHC | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
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