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參數(shù)資料
| 型號： | TMC22071AR1C |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Phono Plug; Leaded Process Compatible:Yes; Gender:Male; Number of Contacts:3 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 125K |
| 代理商： | TMC22071AR1C |
TMC22071A
PRODUCT SPECIFICATION
5
Digital Video
GHSYNC
12
32
CMOS
Horizontal sync output.
When the TMC22071A is locked to
incoming video, the GHSYNC pin provides a negative-going pulse
after the falling edge of the horizontal sync pulse. There is a fixed
number of PXCK clock cycles between adjacent falling edges of
GHSYNC, except following a VCR headswitch.
Vertical sync output.
When the TMC22071A is locked to incoming
video, the GVSYNC pin provides a negative-going edge after the
start of the first vertical sync pulse of a vertical blanking interval.
Composite output bus.
8-bit composite video data is output on this
bus at 1/2 the PXCK rate. During horizontal sync, field ID, subcarrier
frequency, and subcarrier phase are available on this bus.
GVSYNC
13
33
CMOS
CVBS
7-0
11-9, 6-
2
30-28,
25-21
CMOS
m
P l/O
D
0
66
9
TTL
Data l/O port.
Microprocessor data port. All control parameters are
loaded into and read back from the Control Register over this 1-bit
bus.
m
P port control.
Microprocessor address bus. A LOW on this input
loads the l/O Port Shift Register with data from D
0
and CS. A HIGH
transfers the l/O Port Shift Register contents into the Control Register
on the last falling edge of CS.
Chip select.
When CS is HIGH, D
0
is in a high-impedance state and
ignored. When CS is LOW, the microprocessor can read or write D
0
data into the Control Register.
Master reset input.
Bringing RESET LOW forces the internal state
machines to their starting states, loads the Control Register with
default values, and disables outputs. Bringing RESET HIGH restarts
the TMC22071A in its default mode.
Bus read/write control.
When R/W and A
0
are LOW, the
microprocessor can write to the Control Register over D
0
. When R/W
is HIGH and A
0
is LOW, the contents of the Status Register are read
over D
0
.
Interrupt output.
This output is LOW if the internal horizontal phase
lock loop is unlocked with respect to incoming video for 128 or more
lines per field. After lock is established, INT goes HIGH.
HSYNC locked flag.
This output, when HIGH indicates that
incoming horizontal sync has been detected within the
±
16 pixel
window in time established by previous sync pulses. When LOW, it
indicates that incoming horizontal sync has not been found within the
expected time frame. VALID will toggle if the time stability of
incoming video is such that sync positioning varies more than
±
16 pixels or if occasional horizontal sync pulses are missing.
A
0
60
1
TTL
CS
62
5
TTL
RESET
64
7
TTL
R/W
61
4
TTL
INT
67
17
TTL
VALID
14
34
TTL
Pin Definitions
(continued)
Pin Name
Pin Number
68 pin
PLCC
Pin Type
Function
100 pin
MQFP
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