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參數(shù)資料
| 型號： | TMC2192KHC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | 10 Bit Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 46/69頁 |
| 文件大?。?/td> | 457K |
| 代理商： | TMC2192KHC |
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TMC2192
PRODUCT SPECIFICATION
46
REV. 1.0.0 8/13/03
Control Register De
fi
nitions
(continued)
VBI Ped Enable Register (0x17)
7
6
5
4
3
2
1
0
VBIPEDOL
HVA
Reg
17
Bit
7-1
Name
VBIPEDOM
Description
VBI Pedestal Enable, Odd Fields.
VBIPEDOL is the bits 6-0 of VBIPEDO[14:0]. VBIPEDO controls the
addition of pedestal on a line by line basis from line 273 (VBIPEDE[0] =
HIGH) to line 286 (VBIPEDE[13] = HIGH) in the ODD field of NTSC.
VBIPEDO[14] controls the pedestal from line 287 to line 525 inclusive.
Horizontal and Vertical Sync Alignment.
When HVA is LOW, the falling edge of HSIN and VSIN must occur just prior
to the rising edge of PXCK to start an field 1. When HVA is HIGH, VSIN is
allowed to vary from HSIN by
±
32 pixels.
17
0
HVA
Vertical Blanking Interval Enable Register (0x18)
7
6
5
4
3
2
1
0
Reserved
GLKCTL1
GLKCTL0
VBIENF1
Reg
18
18
Bit
7
6
Name
Reserved
GLKCTL1
Description
Genlock Control Register 1.
When GLKCTL1 is LOW, the PALODD bit of the GRS stream is ignored.
When GLKCTL1 is HIGH, the PALODD bit of the GRS stream controls the
PALODD flip of the subcarrier.
Genlock Control Register 0.
When GLKCTL0 is LOW, the Color Frame bit of the GRS stream is ignored.
When GLKCTL0 is HIGH, the Color Frame bit of the GRS stream controls
the field sequence in the FVHGEN.
VBI Active Video Enable, Field 1.
The value of VBIENF1 determines which line blanking stops and active line
for EVEN fields in NTSC starting from line 4 to line 35 or an ODD fields for
PAL starting from line 1 to line 32.
18
5
GLKCTL0
18
4-0
VBIENF
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| TMC2193 | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:10 Bit Encoder |
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| TMC22 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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