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參數(shù)資料
| 型號(hào)： | TMC2111AR3C1 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | Variable-Length Shift Register |
| 中文描述： | 8-BIT, DSP-PIPELINE REGISTER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 69K |
| 代理商： | TMC2111AR3C1 |
PRODUCT SPECIFICATION
TMC2011A/2111A
3
Pin Descriptions – TMC2011A
Pin Name
Power
V
DD
Pin Number
DIP
Pin Function Description
PLCC
7
8
Supply Voltage.
All power and ground lines must be connected.
Ground.
The TMC2011A operates from a single +5V supply. All power
and ground lines must be connected.
The TMC2011A and operates from a single +5V supply.
GND
18
21,22
Data Inputs
DI
7-0
12,11,10,
9,4,3,2,1
14,13,12,
10,5,4,3,2
Data Input.
shift register unchanged. The eight inputs on the TMC2011A are divided
into two groups of four bits to allow mixed delay operation. The lengths of
these two groups are different when the Mode Control (MC) is HIGH (see
Table 1). When MC is LOW both groups have equal delays.
Eight inputs are provided for the data, which pass through the
Data Outputs
DO
7-0
13,14,15,
16,21,22,
23,24
15,16,17,
18,26,27,
28,1
Data Output.
input signals. The amount of the delay is programmable (see Table 1).
The outputs remain valid for a minimum of t
leading edge of CLK. This allow the data to be latched into circuits with
non-zero hold time requirements.
The outputs of the shift register are delayed relative to the
HO
nanoseconds after the
Controls
CLK
8
9
Master Clock.
single master clock. All operations occur on the rising edge of the master
clock.
Length Select.
The length select input is used to determine the register
delay of the TMC2011A. This input is registered and affects the output t
after the clock edge after it is input to the device (see Timing Diagram).
Delay lengths are specified in Table 1.
Mode Control.
The Mode Control is used to select the special 4-bit wide
split mode. When HIGH, the delay on DO
DO
3-0
have the delay specified by the length select. When MC is LOW, all
eight bits have equal delays as specified by the length select.
All inputs and outputs are synchronous and operate from a
L
3-0
19,20,6,5
23,24,7,6
DO
MC
17
20
7-4
is fixed at 18 stages, while
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