參數(shù)資料
型號(hào): TMC2069P7C
廠商: Fairchild Semiconductor Corporation
英文描述: Demonstration Board for the TMC3003 DAC
中文描述: 演示板的TMC3003援
文件頁(yè)數(shù): 11/12頁(yè)
文件大?。?/td> 87K
代理商: TMC2069P7C
TMC2069P7C
PRODUCT SPECIFICATION
11
P
Input Edge Connector Design Notes
Figure 8.
Y/Composite
LPF and
Clamp Circuit
TMC2242
Signal Flow FORWARD
Signal Flow BACKWARD
TMC2072
TMC3003
EPROM
H
L
Low Quality
LPF
Low Quality
LPF
Low Quality
LPF
+5V to -5V
2
H
L
H
L
FPGA
D.C. Supply
SW1
TMC22153
Decoder
Input Logic
10 bit
ADCs
LPFs
SW1
SW2
1
32
1
32
1
32
1
32
T
T
TMC2242
Chrominance
BPF and
Clamp Circuit
Important:
Boards with different revision letters may not be compat-
ible. Damage may occur if they are connected together!
XPXCK is a two times pixel clock fed BACKWARD.
XHSYNC and XVSYNC are timing reference signals fed
BACKWARD.
The MASTER/SLAVE signal states if a board is a
MASTER or a SLAVE board. This signal is fed
FORWARD. A MASTER board produces the PXCK,
HSYNC, and VSYNC signals, and a SLAVE board
expects to receive XPXCK, XHSYNC, XVSYNC, etc .
XDIR is fed FORWARD and controls in which direction
the XRS[3:0] data flows.
PGM_IN is a negative going pulse, logically ANDed with
the onboard program start pulse, for initiating the
programming sequence for components on that board.
Care must be taken to ensure that multiple devices do not
try to drive the RBUS at any given time. Minimum width
of PGM_IN is 1uS.
The RESET pin on the input edge connector should be
connected directly to the RESET pin on the output
connector. A link should be used to connect any pulse to
the RESET line.
The MASTER/SLAVE, XDIR, PGM_IN and RESET pins
on the input edge connector should be connected to +5V
through a 10k pull up resistor.
The CLAMP signal is fed BACKWARD from a MASTER
to a SLAVE board. The CLAMP signal should not be fed
FORWARD.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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