TM16EN64HPU, TM16EN64LPU 16777216 BY 64BIT
TM16EN72HPU, TM16EN72LPU 16777216 BY 72BIT
EXTENDEDDATAOUT DYNAMIC RAM MODULES
SMMS695A AUGUST 1997 REVISED NOVEMBER 1997
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
serial presence detect
The serial-presence-detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD
nonvolatile EEPROM contains various data such as module configuration, DRAM organization, and timing
parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the
remaining 128 bytes are available for customer use. Programming is done through a IIC bus using the clock
(SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard.
See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for
further details.
Tables in this section list the SPD contents as follows:
Table 1TM16EN64HPU
Table 2TM16EN64LPU
Table 3TM16EN72HPU
Table 4TM16EN72LPU
Table 1. Serial-Presence-Detect Data for the TM16EN64HPU
BYTE
FUNCTION DESCRIBED
’16EN64HPU-40
’16EN64HPU-50
’16EN64HPU-60
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written into
serial
memory
during
module
manufacturing
128 bytes
80h
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD memory
device
256 bytes
08h
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM, EDO,
SDRAM)
EDO
02h
EDO
02h
EDO
02h
3
Number of row addresses on this
assembly
12
0Ch
12
0Ch
12
0Ch
4
Number of column addresses on this
assembly
12
0Ch
12
0Ch
12
0Ch
5
Number of module banks on this
assembly
1 bank
01h
1 bank
01h
1 bank
01h
6
Data width of this assembly
64 bits
40h
64 bits
40h
64 bits
40h
7
Data width continuation
00h
8
Voltage
interface
standard
of
this
assembly
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RASx access time of module
tRAC=40 ns
28h
tRAC=50 ns
32h
tRAC=60 ns
3Ch
10
CASx access time of module
tCAC=11ns
0Bh
tCAC=13ns
0Dh
tCAC=15ns
0Fh
11
DIMM configuration type (non-parity,
parity, ECC)
Non-parity
00h
Non-parity
00h
Non-parity
00h
12
Refresh rate / type
15.6
s
00h
15.6
s
00h
15.6
s
00h
13
DRAM width, primary DRAM
x4
04h
x4
04h
x4
04h
14
Error-checking SDRAM data width
N/A
00h
N/A
00h
N/A
00h
62
SPD revision
Rev. 1
01h
Rev. 1
01h
Rev. 1
01h
63
Checksum for bytes 0 62
26
1Ah
38
26h
50
32h
6471
Manufacturer’s JEDEC ID code per
JEP-106E
97h
9700...00h
97h
9700...00h
97h
9700...00h
72
Manufacturing location
TBD
7390
Manufacturer’s part number
TBD
91
Die revision code
TBD
TBD indicates values are determined at manufacturing time and are module dependent.
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